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RISC-V (pronounced "risk-five") is an open-source instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.In contrast to most ISAs, the RISC-V ISA is free and open-source and can be used royalty-free for any purpose, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open architecture[1]ISA, it is significant because it is designed to be useful in a wide range of devices. The instruction set also has a substantial body of supporting software, which avoids a usual weakness of new instruction sets.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers and industry workers outside the university.[2]The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind,[3][4]but without over-architecting for a particular microarchitecture style.[4][5][6][7]As of May 2017, version 2.2 of the userspace ISA is fixed and the privileged ISA is available as draft version 1.10.[4]Contents1Significance2History2.1Predecessors2.2Foundation2.3Awards3Motivating requirements4Software5Adopters5.1Commercial5.2In development6Design6.1ISA base and extensions6.2Register sets6.3Memory access6.4Immediates6.5Subroutine calls, jumps, and branches6.6Arithmetic and logic sets6.7Atomic memory operations6.8Compressed subset6.9Embedded subset6.10Privileged instruction set6.11Bit manipulation6.12Packed SIMD6.13Vector set6.14External debug system7See also8References9Further reading10External linksSignificance[edit]The RISC-V authors aim to provide several CPU designs freely available under a BSD license. Such licenses allow derivative works, such as RISC-V chip designs, to be either open and free, like RISC-V itself, or closed and proprietary.By contrast, commercial chip vendors such as ARM Holdings and MIPS Technologies charge substantial license fees for the use of their patents.[8][9]They also require non-disclosure agreements before releasing documents that describe their designs' advantages and instruction set. The secrecy prevents security auditing.[citation needed]Developing a CPU requires design expertise in several specialties: electronic logic, compilers, and operating systems. It is rare to find this outside of a professional engineering team. The result is that modern, high-quality general-purpose computer instruction sets have not recently been widely available anywhere, or even explained, except in academic settings. Because of this, many RISC-V contributors see it as a unified community effort. This need for a large base of contributors is part of the reason why RISC-V was engineered to fit so many uses.The RISC-V authors also have substantial research and user-experience validating their designs in silicon and simulation. The RISC-V ISA is a direct development from a series of academic computer-design projects. It was originated in part to aid such projects.[4][10]History[edit]Predecessors[edit]The term "RISC" dates from about 1980.[11]Before this, there was some knowledge that simpler computers could be effective, but the design principles were not widely described. Simple, effective computers have always been of academic interest.Academics created the RISC instruction set DLX for the first edition of Computer Architecture: A Quantitative Approach in 1990. David Patterson was an author, and later assisted RISC-V. However DLX was for educational use. Academics and hobbyists implemented it using field-programmable gate arrays, but it was not a commercial success.ARM CPUs, version 2 and earlier, had a public-domain instruction set, and it is still supported by GCC, a popular free-software compiler. Three open-source cores exist for this ISA, but they have not been manufactured.[12][13]OpenRISC is an open-source ISA based on DLX, with associated RISC designs. It is fully supported with GCC and Linux implementations. However, it has few commercial implementations.Foundation[edit]Krste Asanović at University of California, Berkeley, found many uses for an open-source computer system. In 2010 he decided to develop and publish one in a "short, three-month project over the summer". The plan was to help both academic and industrial users.[10]David Patterson at Berkeley also aided the effort. Patterson originally identified the properties of Berkeley RISC,[11]and RISC-V is one of his long series of cooperative RISC research projects. Early funding was from DARPA.[4]A partial list of organizations that support the RISC-V Foundation includes: AMD,[14]Andes Technology,[15]BAE Systems, Berkeley Architecture Research, Bluespec, Inc., Cortus, Google, GreenWaves Technologies, Hewlett Packard Enterprise, Huawei, IBM, Imperas Software, ICT, IIT Madras, Lattice Semiconductor, Mellanox Technologies, Microsemi, Micron, Nvidia, NXP, Oracle, Qualcomm, Rambus Cryptography Research, Western Digital, and SiFive.[16][17]Awards[edit]2017: The Linley Group's Analyst's Choice Award for Best Technology (for the instruction set)[18]Motivating requirements[edit]The designers claim that the instruction set is the main interface in a computer, because it lies between the hardware and the software. If a good instruction set was open, available for use by all, it should dramatically reduce the cost of software by permitting far more reuse. It should also increase competition among hardware providers, who can use more resources for design and less for software support.[10]The designers assert that new principles are becoming rare in instruction set design, as the most successful designs of the last forty years have become increasingly similar. Of those that failed, most did so because their sponsoring companies failed commercially, not because the instruction sets were poor technically. So, a well-designed open instruction set designed using well-established principles should attract long-term support by many vendors.[10]Most prior open ISAs used the GNU General Public License (GPL), encouraging users to open their implementations to copying and use by others.Unlike other academic designs which are optimized only for simplicity of exposition, the designers state that the RISC-V instruction set is for practical computers. It is said to have features to increase computer speed, yet reduce cost and power use. These include a load/store architecture, bit patterns to simplify the multiplexers in a CPU, simplified standards-based floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign-extension. Sign extension is said to often be on the critical timing path.[4]The instruction set is designed for a wide range of uses. It supports three word-widths, 32, 64, and 128 bits, and a variety of subsets. The definitions of each subset vary slightly for the three word-widths. The subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale rack-mounted parallel computers.The instruction set is variable-width and extensible, so that more encoding bits can always be added. Space for the 128-bit stretched version of the ISA was reserved, because 60 years of industry experience has shown that the most unrecoverable error in instruction set design is a lack of memory address space. As of 2016, the 128-bit ISA remains undefined intentionally, because there is yet so little practical experience with such large memory systems.[4]However, RISC-V also supports the designers' academic uses. The simplicity of the integer subset permits basic student exercises. The integer subset is a simple ISA enabling software to control research machines. The variable-length ISA enables extensions for both student exercises and research.[4]The separated privileged instruction set permits research in operating system support, without redesigning compilers.[19]RISC-V's open intellectual property allows its designs to be published, reused, and modified.[4]Software[edit]A normal problem for a new instruction set is a lack of CPU designs and software.The RISC-V website has a specification for user-mode instructions, and a preliminary specification for a general-purpose privileged instruction set, to support operating systems.[20]There are several open-sourced CPU designs, including the 64-bit Berkeley Out of Order Machine (BOOM),[21]64-bit Rocket,[22]five 32-bit Sodor CPU designs from Berkeley,[23]picorv32 by Clifford Wolf, scr1 from Syntacore, PULPino (Riscy and Zero-Riscy) from ETH Zürich / University of Bologna,[24]and others. The three-stage Sodor CPU appears apt for a small embedded CPU. Rocket may suit compact, low-power intermediate computers such as personal devices. BOOM utilizes much of the infrastructure created for Rocket, and may be usable for personal, supercomputer and warehouse-scale computers. Both picorv and scr1 are 32-bit MCU class RV32IMC implementations in Verilog. The cores in PULPino implement a simple RV32IMC ISA for micro-controllers (Zero-Riscy) or a more powerful RV32IMFC ISA with custom DSP extensions for embedded signal processing.The design software includes a design compiler, Chisel,[25]which can reduce the designs to Verilog for use in devices. The website includes verification data for testing core implementations.Available RISC-V software tools include a GNU Compiler Collection (GCC) toolchain (with GDB, the debugger), an LLVM toolchain, the OVPsim simulator (and library of RISC-V Fast Processor Models), the Spike simulator, and a simulator in QEMU.Operating system support exists for the Linux kernel, FreeBSD, and NetBSD, but the supervisor-mode instructions are unstandardized as of 10 November 2016,[19]so this support is provisional. The preliminary FreeBSD port to the RISC-V architecture was upstreamed in February 2016, and shipped in FreeBSD 11.0.[26][27]Ports of Debian[28]and Fedora[29]are stabilizing. There is a port of U-Boot.[30]UEFI Spec v2.7 has defined the RISC-V binding and a tianocore port has been done by HPE engineers and is expected to be upstreamed. There is a preliminary port of the seL4 microkernel.[31][32]There is also a simulator to run a RISC-V Linux system on a web browser using JavaScript.[citation needed]Adopters[edit]Commercial[edit]SiFive, a company established specifically for developing RISC-V hardware, has processor models released in 2017.[33][34] These include a quad-core RISC-V SoCa quad-core, 64-bit SoC.[35]Syntacore,[36] a founding member of the RISC-V Foundation and one of the first commercial RISC-V IP vendors, develops and licenses family of RISC-V IP since 2015. As of 2018, product line includes eight 32 and 64 bit cores, including open-source SCR1 MCU core.[37] First commercial SoCs, based on the Syntacore IP were demonstrated in 2016.[38]Andes Technology Corporation, a founding member of the RISC-V Foundation[39] which joined the consortium in 2016, released its first two RISC-V cores in 2017. The cores, the N25 and NX25, come with a complete design ecosystems and a number of RISC-V partners. Andes is actively driving the development of RISC-V ecosystem and expects to release several new RISC-V products in 2018.Codasip and UltraSoC have developed fully supported intellectual property for RISC-V embedded SOCs that combine Codasip's RISC-V cores and other IP with UltraSoC's debug, optimization and analytics.[40]Imperas has developed a family of fast processor models for the different subsets of RV32GC and RV64GC ISA variants that are part of the OVPsim instruction accurate simulator distributions used for embedded software development.GreenWaves Technologies announced the availability of GAP8, a 32-bit 1 controller plus 8 compute cores, 32-bit SoC and developer board in February 2018. Their GAPuino GAP8 development board started shipping in May 2018.[41][42][43]Hex Five announced general availability MultiZone Security - the first RISC-V Trusted Execution Environment utilizing the standard RISC-V ISA and privileged mode extensions.[44]CloudBEAR is a processor IP company that develops its own RISC-V cores for a range of applications.[45]In development[edit]Indian Institute of Technology Madras is developing six RISC-V open-source CPU designs for six distinct uses, from a small 32-bit CPU for the Internet of Things(IoT) to large, 64-bit CPUs designed for warehouse-scale computers such as server farms based on RapidIO and Hybrid Memory Cube technologies.[6][46]Nvidia plans to use RISC-V to replace their Falcon processor on their GeForce graphics cards.[47]ASTC developed a RISC-V CPU for embedded ICs.[48]Adapteva plans to use RISC-V, in a successor to their manycore accelerator product[49]lowRISC[50] is a non profit project that aims to implement a fully open-source system on a chip (SoC) based on the 64-bit RISC-V ISA.Computer Laboratory, University of Cambridge, in collaboration with the FreeBSD Project, has ported the FreeBSD operating system to 64-bit RISC-V to use as a hardware-software research platform.[27]ETH Zurich and the University of Bologna have cooperatively developed the open-source RISC-V PULPino processor[51] as part of the PULP (Parallel Ultra-Low Power) project for energy-efficient IoT computing.[52]Western Digital announced a plan to embed RISC-V processors in their future products.[53]Esperanto Technologies has disclosed that they are developing three RISC-V based processors: ET-Maxion – a high-performance RISC-V core, ET-Minion – an energy-efficient RISC-V core, and ET-Graphics – a RISC-V-based graphics processor.[54]Design[edit]ISA base and extensions[edit]RISC-V has a modular design, consisting of alternative base parts, with additional optional extensions. The ISA base and its extensions are developed in a collective effort between industry, the research community and educational institutions. The base specifies instructions (and their encoding), control flow, registers (and their sizes), memory and addressing, logic (i.e., integer) manipulation, and ancillaries. The base by itself can implement a simplified general-purpose computer, with full software support, including a general-purpose compiler.The standard extensions are specified to work with all of the standard bases, and with each other without conflict.Many RISC-V computers might implement the compact extension to reduce power consumption, code size, and memory usage.[4]There are also future plans to support hypervisors and virtualization.[19]Together with a supervisor instruction set extension, S, an RVGC defines all instructions needed to conveniently support a Unix-style operating system.NameDescriptionVersionStatus[a]BaseRV32IBase Integer Instruction Set, 32-bit2.0FrozenRV32EBase Integer Instruction Set (embedded), 32-bit, 16 registers1.9OpenRV64IBase Integer Instruction Set, 64-bit2.0FrozenRV128IBase Integer Instruction Set, 128-bit1.7OpenExtensionMStandard Extension for Integer Multiplication and Division2.0FrozenAStandard Extension for Atomic Instructions2.0FrozenFStandard Extension for Single-Precision Floating-Point2.0FrozenDStandard Extension for Double-Precision Floating-Point2.0FrozenGShorthand for the base and above extensionsN/AN/AQStandard Extension for Quad-Precision Floating-Point2.0FrozenLStandard Extension for Decimal Floating-Point0.0OpenCStandard Extension for Compressed Instructions2.0FrozenBStandard Extension for Bit Manipulation0.36OpenJStandard Extension for Dynamically Translated Languages0.0OpenTStandard Extension for Transactional Memory0.0OpenPStandard Extension for Packed-SIMD Instructions0.1OpenVStandard Extension for Vector Operations0.2OpenNStandard Extension for User-Level Interrupts1.1Open^ Frozen parts are expected to have their final feature set and to receive only clarifications before being ratified.To tame the combinations of functionality that may be implemented, a nomenclature is defined to specify them.[4]The instruction set base is specified first, coding for RISC-V, the register bit-width, and the variant; e.g., RV64I or RV32E. Then follows letters specifying implemented extensions in canonical order (as above). The base, extended integer and floating point calculations, and synchronisation primitives for multi-core computing, the base and extensions MAFD, are considered to be necessary for general purpose computation, and thus have the shorthand, G.A small 32-bit computer for an embedded system might be RV32EC. A large 64-bit computer might be RV64GC; i.e., shorthand for RV64IMAFDC.A naming scheme with Zxxx for standard extensions and Yxxx for non-standard (vendor-specific) extensions has been proposed. For example, the Ztso extension for total store ordering, an alternative memory consistency model to weak memory ordering is under discussion.[55]Register sets[edit]RISC-V has 32 (or 16 in the embedded variant) integer registers, and, when the floating point extension is implemented, 32 floating-point registers. Except for memory access instructions, instructions address only registers.The first integer register is a zero register, and the remainder are general purpose registers. A store to the zero register has no effect, and a read always provides 0. Using the zero register as a placeholder makes for a simpler instruction set. E.g., move rx to ry becomes add r0 to rx and store in ry.[4]Control and status registers exist, but user-mode programs can access only those used for performance-measurement and floating point management.There are no instructions to save and restore multiple registers. Those were thought to be unnecessary, too complex and perhaps too slow.[4]Memory access[edit]Like many RISC designs, RISC-V is a load/store architecture; instructions address only registers, with load and store instructions conveying to and from memory.[4]Memory consists of and is addressed as 8-bit bytes, with words being in little-endian order.[4]Words, up to the register size, can be accessed with the load and store instructions.Accessed memory addresses need not be aligned to their word-width, but accesses to aligned addresses will always be the fastest. As, for example, simple CPUs may implement unaligned accesses with slow software emulation driven from an alignment failure interrupt.[4]RISC-V manages memory systems that are shared between CPUs or threads by ensuring a thread of execution always sees its memory operations in the programmed order. But between threads and I/O devices, RISC-V is simplified: It doesn't guarantee the order of memory operations, except by specific instructions, such as fence.A fence instruction guarantees that the results of predecessor operations are visible to successor operations of other threads or I/O devices. fence can guarantee the order of combinations of both memory and memory-mapped I/O operations. E.g. it can separate memory read and write operations, without affecting I/O operations. Or, if a system can operate I/O devices in parallel with memory, fence doesn't force them to wait for each other. A single CPU with one thread may decode fence as nop.Like many RISC instruction sets (and indeed some complex instruction set computer (CISC) instruction sets, such as x86 and IBM System/360 families), RISC-V lacks address-modes that write back to the registers. For example, it does not do auto-incrementing.[4]RISC-V is little-endian to resemble other familiar, successful computers, for example, x86. This also reduces a CPU's complexity and costs slightly because it reads all sizes of words in the same order. For example, the RISC-V instruction set decodes starting at the lowest-addressed byte of the instruction. The specification leaves open the possibility of non-standard big-endian or bi-endian systems.[4]Some RISC CPUs (such as MIPS, PowerPC, DLX, and Berkeley's RISC-I) place 16 bits of offset in the loads and stores. They set the upper 16 bits by a "load upper word" instruction. This permits upper-halfword values to be set easily, without shifting bits. However, most use of the upper half-word instruction makes 32-bit constants, like addresses. RISC-V uses a SPARC-like combination of 12-bit offsets and 20-bit "set upper" instructions. The smaller 12-bit offset helps compact, 32-bit load and store instructions select two of 32 registers yet still have enough bits to support RISC-V's variable-length instruction coding.[4]Immediates[edit]RISC-V handles 32-bit constants and addresses with instructions that set the upper 20 bits of a 32-bit register. Load upper immediate lui loads 20 bits into bits 31 through 12. Another instruction, auipc generates the same 20 upper address bits by adding an offset to the program counter and storing the result into a base register. This permits position-independent code to have 32-bit addresses relative to the program counter. The base register can be used as-is with the 12-bit offsets of the loads and stores. If needed, addi can set the lower 12-bits of a register. In 64-bit ISAs,lui and auipc sign-extend the result to 64 bits.[4]Some fast CPUs may interpret combinations of instructions as single "fused" instructions. lui or auipc may be good candidates to fuse with loads or stores.Subroutine calls, jumps, and branches[edit]RISC-V's subroutine call jal (jump and link) places its return address in a register. This is faster in many computer designs, because it saves a memory access compared to systems that push a return address directly on a stack in memory. jal has a 20-bit signed (2's complement) offset. The offset is multiplied by 2, then added to the PC to generate a relative address to a 32-bit instruction. If the result is not at a 32-bit address (i.e. evenly divisible by 4), the CPU may force an exception.[4]RISC-V CPUs jump to calculated addresses using a "jump and link-register", jalr instruction. jalr is similar to jal, but gets its destination address by adding a 12-bit offset to a base register. (In contrast,jal adds a larger 20-bit offset to the PC.)jalr's bit format is like the register-relative loads and stores. Like them, jalr can be used with the instructions which set the upper 20 bits of a base register in order to make 32-bit branches, either to an absolute address (using lui) or a PC-relative one (using auipc for position-independent code). (Using a constant zero base address allows single-instruction calls to a small (the offset), fixed positive or negative address.)RISC-V recycles jal and jalr to get unconditional 20-bit PC-relative jumps and unconditional register-based 12-bit jumps. Jumps just make the linkage register 0 so that no return address is saved.[4]RISC-V also recycles jalr to return from a subroutine: To do this, jalr's base register is set to be the linkage register saved by jal or jalr. jalr's offset is zero and the linkage register is zero, so that there is no offset, and no return address is saved.Like many RISC designs, in a subroutine call, a RISC-V compiler must use individual instructions to save registers to the stack at the start, and then restore these from the stack on exit. RISC-V has no "save multiple" or "restore multiple" register instructions. These were thought to make the CPU too complex, and possibly slow, as well.[56]This can take more code space. Designers planned to reduce code size with library routines to save and restore registers.[57]RISC-V has no condition code register or carry bit. The designers believed that condition codes make fast CPUs more complex by forcing interactions between instructions in different stages of execution. This choice makes multiple-precision arithmetic more complex. Also, a few numerical tasks need more energy.[4]Instead, RISC-V has short branches that perform comparisons: equal, not-equal, less-than, unsigned less-than, greater-than and unsigned greater-than. Ten comparison-branch operations are implemented with only six instructions, by reversing the order of operands in the assembler. For example, "branch if greater than" can be done by "less than or equal" with a reversed order of operands.[4]The comparing branches have a twelve-bit signed range, and jump relative to the PC.[4]RISC-V's ISA requires default branch predictions for CPUs: Backward conditional branches should be predicted "taken". Forward conditional branches predict "not taken". The predictions are easy to decode in a pipelined CPU: Branch addresses are signed numbers added to the PC. Backward branches have negative two's complement addresses, and therefore have a one in the most significant bit of the address. Forward branches have a zero. The most significant bit is in a fixed location in the operation code in order to speed up the pipeline. Complex CPUs can add branch predictors to work well even with unusual data or situations.The ISA manual recommends that software be optimized to avoid branch stalls by using the default branch predictions. This reuses the most significant bit of the signed relative address as a "hint bit" to tell whether the conditional branch will be taken or not. So, no other hint bits are needed in the operation codes of RISC-V branches. This makes more bits available in the branch operation codes. Simple, inexpensive CPUs can merely follow the default predictions and still perform well with optimizing compilers. Compilers can still perform statistical path optimization, if desired.[4]To avoid unnecessary loading of branch prediction electronics, (and therefore unnecessary pipeline stalls) the comparing branch codes should never be used for unconditional jumps.[4]RISC-V does not support predication (the conditional execution of instructions) as its designers claim that CPUs without predication are easier to design, and optimizing compilers are less likely to mistakenly use predication where it should not be used. The designers claim that very fast, out-of-order CPU designs do predication anyway, by doing the comparison branch and conditional code in parallel, then discarding the unused path's effects. They also claim that even in simpler CPUs, predication is less valuable than branch prediction, which can prevent most stalls associated with conditional branches. Code without predication is larger, with more branches, but they also claim that a compressed instruction set (such as RISC-V's set "C") solves that problem in most cases.[4]Many RISC designs have included a branch delay slot, a position after a branch instruction that can be filled with an instruction which is executed whether or not the branch is taken. This feature can improve the performance of pipelined CPUs by absorbing some of the time wasted if a CPU mispredicts the operation of a conditional branch, and the CPU's pipeline stalls. RISC-V omits a branch delay slot because it complicates multicycle CPUs, superscalar CPUs, and long pipelines. Dynamic branch predictors have succeeded well enough to reduce the need for delayed branches.[4]Arithmetic and logic sets[edit]RISC-V segregates math into a minimal set of integer instructions (set "I") with add, subtract, shift, bit-wise logic and comparing-branches. These can simulate most of the other RISC-V instruction sets with software. (The atomic instructions are a notable exception.) RISC-V currently lacks the "count leading zero" and bit-field operations normally used to speed software floating-point in a pure-integer processor.The integer multiplication instructions (set "M") includes signed and unsigned multiply and divide. Double-precision integer multiplies and divides are included, as multiplies and divides that produce the "high word" of the result. The ISA document recommends that implementors of CPUs and compilers "fuse" a standardized sequence of high and low multiply and divide instructions to a single operation if possible.[4]The floating-point instructions (set "F") includes single-precision arithmetic and also comparison-branches similar to the integer arithmetic. It requires an additional set of 32 floating-point registers. These are separate from the integer registers. The double-precision floating point instructions (set "D") generally assume that the floating-point registers are 64-bit (i.e. double-width), and the "F" subset is coordinated with the "D" set. A quad-precision 128-bit floating-point ISA ("Q") is also defined. RISC-V computers without floating-point can use a floating-point software library.[4]RISC-V does not cause exceptions on arithmetic errors, including overflow, underflow, subnormal and divide by zero. Instead, both integer and floating-point arithmetic produce reasonable default values and set status bits. Divide-by-zero can be discovered by a single branch after the division. The status bits can be tested by an operating system or periodic interrupt.[4]Atomic memory operations[edit]RISC-V supports computers that share memory between multiple CPUs and threads. RISC-V's standard memory consistency model is release consistency. That is, loads and stores may generally be reordered, but some loads may be designated as "acquire" operations which must precede later memory accesses, and some stores may be designated as "release" operations which must follow earlier memory accesses.[4]The base instruction set includes minimal support in the form of a fence instruction to enforce memory ordering. Although this is sufficient (fence r, rw provides "acquire" and fence rw, w provides "release"), combined operations can be more efficient.[4]The atomic memory operation extension supports two types of atomic memory operations for release consistency. First, it provides general purpose "load-reserved" lr and "store-conditional" sc instructions. lr performs a load, and tries to reserve that address for its thread. A later store-conditional sc to the reserved address will be performed only if the reservation is not broken by an intervening store from another source. If the store succeeds, a zero is placed in a register. If it failed, a non-zero value indicates that software needs to retry the operation. In either case, the reservation is released.[4]The second group of atomic instructions perform read-modify-write sequences: a load (which is optionally a load-acquire) to a destination register, then an operation between the loaded value and a source register, then a store of the result (which may optionally be a store-release). Making the memory barriers optional permits combining the operations. The optional operations are enabled by "acquire" and "release" bits which are present in every atomic instruction. RISC-V defines nine possible operations: swap (use source register value directly); add; bitwise and, or, and exclusive-or; and signed and unsigned minimum and maximum.[4]A system design may optimize these combined operations more than lr and sc. For example, if the destination register for a swap is the constant zero, the load may be skipped. If the value stored is unmodified since the load, the store may be skipped.[4]The IBM System/370 and its successors including z/Architecture, and x86, both implement a compare-and-swap (cas) instruction, which tests and conditionally updates a location in memory: if the location contains an expected old value, cas replaces it with a given new value; it then returns an indication of whether it made the change. However, a simple load-type instruction is usually performed before the cas to fetch the old value. The classic problem is that if a thread reads (loads) a value "A", calculates a new value "C", and then uses (cas) to replace "A" with "C", it has no way to know whether concurrent activity in another thread has replaced "A" with some other value "B" and then restored the "A" in between. In some algorithms (e.g., ones in which the values in memory are pointers to dynamically allocated blocks), this ABA problem can lead to incorrect results. The most common solution employs a "double-wide cas" instruction to update both the pointer and an adjacent counter; unfortunately, such an instruction requires a special instruction format to specify multiple registers, performs several reads and writes, and can have complex bus operation.[4]The lr/sc alternative is more efficient. It usually requires only one memory load, and minimizing slow memory operations is desirable. It's also exact: it controls all accesses to the memory cell, rather than just assuring a bit pattern. However, unlike cas, it can permit livelock, in which two or more threads repeatedly cause each other's instructions to fail. RISC-V guarantees forward progress (no livelock) if the code follows rules on the timing and sequence of instructions: 1) It must use only the "I" subset. 2) To prevent repetitive cache misses, the code (including the retry loop) must occupy no more than 16 consecutive instructions. 3) It must not include any system or fence instructions, or taken backward branches between the lr and sc. 4) The backward branch to the retry loop must be to the original sequence.[4]The specification gives examples of how to use this subset to lock a data structure.[4]Compressed subset[edit]The standard RISC-V ISA specifies that all instructions are 32 bits. This makes for a particularly simple implementation, but like other RISC processors with such an instruction encoding, results in larger code size than in other instruction sets.[4][56]To compensate, RISC-V's "32-bit" instructions are actually 30 bits; ​3⁄4 of the opcodespace is reserved for an optional (but recommended) variable-length "compressed" instruction set, RVC, that includes 16-bit instructions. Like ARM's Thumb and the MIPS16, the compressed instructions are simply aliases for a subset of the larger instructions. Unlike ARM's Thumb or the MIPS compressed set, space was reserved from the beginning so there is no separate operating mode. Standard and compressed instructions may be intermixed freely.[4][56](letter "C")[57]Because (like Thumb-1 and MIPS16) the compressed instructions are simply alternate encodings (aliases) for a selected subset of larger instructions, the compression can be implemented in the assembler, and it is not essential for the compiler to even know about it.A prototype of RVC was tested in 2011.[56]The prototype code was 20% smaller than an x86 PC and MIPS compressed code, and 2% larger than ARM Thumb-2code.[56]It also substantially reduced both the needed cache memory and the estimated power usage of the memory system.[56]The researcher intended to reduce the code's binary size for small computers, especially embedded computer systems. The prototype included 33 of the most frequently used instructions, recoded as compact 16-bit formats using operation codes previously reserved for the compressed set.[56]The compression was done in the assembler, with no changes to the compiler. Compressed instructions omitted fields that are often zero, used small immediate values or accessed subsets (16 or 8) of the registers. addi is very common and often compressible.[56]Much of the difference in size compared to Arm's Thumb set occurred because RISC-V, and the prototype, have no instructions to save and restore multiple registers. Instead, the compiler generated conventional instructions that access the stack. The prototype RVC assembler then often converted these to compressed forms that were half the size. However, this still took more code space than the ARM instructions that save and restore multiple registers. The researcher proposed to modify the compiler to call library routines to save and restore registers. These routines would tend to remain in a code cache and therefore run fast, though probably not as fast as a save-multiple instruction.[56]Embedded subset[edit]An instruction set for the smallest "embedded" CPUs (set "E") is reduced in other ways: Only 16 of the 32-bit integer registers are supported. Floating-point instructions should not be supported (the specification forbids it as uneconomical), so a floating-point software library must be used.[4]The compressed set "C" is recommended. The privileged instruction set supports only machine mode, user mode and memory schemes that use base-and-bound address relocation.[19]There is also discussion of a microcontroller profile for RISC-V, to ease development of deeply embedded systems. It centers on faster, simple C-language support for interrupts, simplified security modes and a simplified POSIX application binary interface.[58]Correspondents have also proposed smaller, non-standard, 16-bit "RV16E" ISAs: One would use 16 × 16-bit integer registers, using the standard "EIMC" ISAs (including 32-bit instructions.)[59]Another proposal would only use the 16-bit "C" instructions with 8 × 16-bit registers. A full RV16EG was said to be possible with a completely recoded ISA.[60]Privileged instruction set[edit]The privileged instruction set specification of RISC-V is currently (July 2017) preliminary.[19]RISC-V's ISA includes a separate privileged instruction set specification.Version 1.10 of the specification supports several types of computer systems:Systems that have only "machine mode", perhaps for embedded systems,Systems with both machine mode (for the supervisor) and user-mode, perhaps to implement Linux.Systems with machine-mode, hypervisors, multiple supervisors, and user-modes under each supervisor.These correspond roughly to systems with up to four "rings" of privilege and security, at most: machine, hypervisor, supervisor and user. Each layer also is expected to have a thin layer of standardized supporting software that communicates to a more-privileged layer, or hardware.[19]The overall plan for this ISA is to make the hypervisor mode orthogonal to the user and supervisor modes.[61]The basic feature is a configuration bit that either permits supervisor-level code to access hypervisor registers, or causes an interrupt on accesses. This bit lets supervisor mode directly handle the hardware needed by a hypervisor. This simplifies a type 2 hypervisor, hosted by an operating system. This is a popular mode to run warehouse-scale computers. To support type 1, unhosted hypervisors, the bit can cause these accesses to interrupt to a hypervisor. The bit simplifies nesting of hypervisors, in which a hypervisor runs under a hypervisor. It's also said to simplify supervisor code by letting the kernel use its own hypervisor features with its own kernel code. As a result, the hypervisor form of the ISA supports five modes: machine, supervisor, user, supervisor-under-hypervisor and user-under-hypervisor.The privileged instruction set specification explicitly defines "hardware threads", or "harts". Multiple hardware threads are a common practice in larger, more powerful computers. When one thread is stalled, waiting for memory, others can often proceed. Hardware threads can help make better use of the large number of registers and execution units in large CPUs. Finally, hardware threads can be a simple, powerful way to handle interrupts: No saving or restoring of registers is required, simply executing a different hardware thread. The only hardware thread required in a RISC-V computer is thread zero.[19]The existing control and status register definitions support RISC-V's error and memory exceptions, and a small number of interrupts. For larger systems, the specification also defines an interrupt controller. Interrupts always start at the highest-privileged machine level, and the control registers of each level have explicit "forwarding" bits to route interrupts to less-privileged code. For example, the hypervisor need not include software that executes on each interrupt to forward an interrupt to an operating system. Instead, on set-up, it can set bits to forward the interrupt.[19]Several memory systems are supported in the specification. Physical-only is suited to the smallest embedded systems. There are also three UNIX-style virtual memorysystems for memory cached in mass-storage systems. The virtual memory systems have three sizes, with addresses sized 32, 39 and 48-bits. All virtual memory systems support 4 KiB pages, multilevel page-table trees and use very similar algorithms to walk the page table trees. All are designed for either hardware or software page-table walking. To optionally reduce the cost of page table walks, super-sized pages may be leaf pages in higher levels of a system's page table tree. SV32 has a two layer page table tree and supports 4 MiB superpages. SV39 has a three level page table, and supports 2 MiB superpages and 1 GiB gigapages. SV48 is required to support SV39. It also has a 4-level page table and supports 2 MiB superpages, 1 GiB gigapages, and 512 GiB terapages. Superpages are aligned on the page boundaries for the next-lowest size of page.[19]Bit manipulation[edit]Substantial work was done to produce a preliminary, though unapproved, bit manipulation ("B") ISA for RISC-V. Done well, a bit manipulation subset can aid cryptographic, graphic and mathematical operations. The criteria for inclusion documented in the draft were compliance with RV5 philosophies and ISA formats, substantial improvements in code density or speed (i.e. at least a 3-for-1 reduction in instructions), and substantial real-world applications, including preexisting compiler support. Version 0.36 included[62]uncontroversial instructions to count leading zeros, count one bits, perform 'and' with complement, shift ones, rotate, a generalized bit-reverse and shuffle, byte swaps, bit extracts and deposits, and some bit manipulation additions for the compressed set (not, neg and reverse). It also includes a controversial proposal for bit-field extract and place, using a nonstandard 48-bit instruction format.Packed SIMD[edit]For simple, cost-reduced RISC-V systems, there is a proposal to use the floating-point registers' bits to perform parallel SIMD sub-word arithmetic. This is widely used to accelerate multimedia and other digital signal processing.[4]This ISA is (as of 2016) undefined, but could resemble PA-RISC's multimedia instructions. Besides its native 64-bit math, the PA-RISC MAX2 CPU could do arithmetic on four 16-bit subwords at a time, with several overflow methods. It also could move subwords to different positions. PA-RISC's MAX2 was intentionally simplified. It lacked support for 8-bit or 32-bit subwords. The 16-bit subword size was chosen to support most digital signal processing tasks. These instructions were inexpensive to design and build. However, they increased the CPU's performance on digital signal processing tasks by 48-fold or more, enabling practical real-time video codecs in 1995.[63][64]Vector set[edit]The proposed vector processing instruction set may make the packed SIMD set obsolete. The designers hope to have enough flexibility so that a CPU can implement vector instructions in a standard processor's registers. This would enable minimal implementations with similar performance to a multimedia ISA, (as above.) However, a true vector coprocessor could execute the same code with higher performance.[65]The vector processing proposal is currently (29 June 2015) a conservative, flexible design of a general-purpose mixed-precision vector processor (suitable for executing compute kernels). Code would port easily to CPUs with differing vector lengths, ideally without recompiling.[65]In contrast, short-vector SIMD extensions are less convenient. These are used in x86, ARM and PA-RISC. In these, a change in word-width forces a change to the instruction set to expand the vector registers (in the case of x86, from 64-bit MMX registers to 128-bit SSE, to 256-bit AVX, and AVX-512). The result is not only a growing instruction set, but also a need to port working code to the new instructions.In the RISC-V vector ISA, rather than fix the vector length in the architecture, an instruction (setvl) is available which takes a requested size and sets the vector length to the minimum of the hardware limit and the requested size. So, the RISC-V proposal is more like a Cray's long-vector design. That is, each vector in up to 32 vectors is the same length.[65]The application specifies the total vector width it requires, and the processor determines the vector length it can provide with available on-chip resources. This takes the form of an instruction (vsetcfg) with four immediate operands, specifying the number of vector registers of each available width needed. The total must be no more than the addressable limit of 32, but may be less if the application does not require them all. The vector length is limited by the available on-chip storage divided by the number of bytes of storage needed for each entry. (Added hardware limits may also exist, which in turn may permit SIMD-style implementations.)[65]Outside of vector loops, the application can request zero vector registers, saving the operating system the work of preserving them on context switches.[65]The vector length is not only architecturally variable, but designed to vary at run time also. To achieve this flexibility, the instruction set is likely to use variable-width data paths and variable-type operations using polymorphic overloading.[65]The plan is that these can reduce the size and complexity of the ISA and compiler.[65]Recent experimental vector processors with variable-width data paths also show profitable increases in operations per: second (speed), area (lower cost), and watt (longer battery life).[66]Unlike a typical modern graphics processing unit, there are no plans to provide special hardware to support branch predication. Instead, lower cost compiler-based predication will be used.[65][67]External debug system[edit]There is a preliminary specification for RISC-V's hardware-assisted debugger. The debugger will use a transport system such as Joint Test Action Group (JTAG) or Universal Serial Bus (USB) to access debug registers. A standard hardware debug interface may support either a "standardized abstract interface" or "instruction feeding".[68][69]The exact form of the "abstract interface" remains undefined (January 2017), but proposals include a memory mapped system with standardized addresses for the registers of debug devices or a command register and a data register accessible to the communication system.[68]Correspondents claim that similar systems are used by Freescale's BDM for some CPUs, ARM, OpenRISC and Aeroflex's LEON.[68]In "instruction feeding", the CPU will process a debug exception to execute individual instructions written to a register. This may be supplemented with a data-passing register and a module to directly access the memory. Instruction feeding lets the debugger access the computer exactly as software would. It also minimizes changes in the CPU, and adapts to many types of CPU. This was said to be especially apt for RISC-V because RISC-V is explicitly designed for many types of computers. The data-passing register allows a debugger to write a data-movement loop to RAM, and then execute the loop to move data into or out of the computer at a speed near the maximum speed of the debug system's data channel.[68]Correspondents claim that similar systems are used by MIPs, Intel Quark, Tensilica's Xtensa and for FreescalePower CPUs' BDM.[68]

If you converted all of the CO2 on earth using some device the following realities would occur.The Oxygen content of the air would be raised a total of 0.041%. That isn’t even enough to notice. Such a conversion would immediately kill all plants and end all life on earth.CO2 is NOT a pollutant and is NOT dangerous. Even at levels 15 times current levels there is no prospect of any environmental damages from CO2 and that amount could not be achieved by modern emission levels in something like 3 centuries.Planting Trees is a good idea but it is not to remove CO2.CO2 as a gas does a process known as Light Amplification by Stimulated Emission of Radiation. (LASER) This process is very simple and does not involve any device. It is used in CO2 lasers but the process is entirely natural.This process takes CO2 molecules that are heated up and causes them to radiate energy once struck by IR to emit more IR in the same direction as the original IR emission. This is stunningly fast. This LASER pumping cools the atmosphere and does not retain heat.There is no such thing as a CO2 based “Greenhouse Effect”. The claims and of CO2 being a “Greenhouse Gas” is a marketing lie. It has no reality. A greenhouse only does 2 things.It stops the windIt does provide as a minor effect a selective frequency mirror to IR and transmits visible light.No CO2 does not do either effect and has no relationship to this.This was tested by scientists at UC Berkeley in 2016 and the results of attempting to use CO2 for the selective frequency mirror for insulation in thermopane glass systems was found counterproductive.Industry Experts: CO2 Worse Than Useless in Trapping Heat/Delaying Cooling | PSI IntlThus the entire claim about CO2 is bogus because CO2 is actually a refrigerant gas and does not produce any greenhouse effect. It actually cools the earth.Industry Experts: CO2 Worse Than Useless In Trapping Heat/Delaying CoolingPublished onApril 7, 2016Written by John O'Sullivan (HT: Alan Siddons)Does carbon dioxide have the physical properties of heat trapping/delayed cooling as alleged by climate scientists? Well, according to experiments conducted by experts in the ‘hard’ sciences at Lawrence Berkeley Laboratory CO2 just doesn’t do what climate science says it does.For three decades now academics have been warning governments and scaring the bejesus out of policymakers about the ‘dangerous’ warming properties of CO2 and other ‘greenhouse gases’ if we allow human emissions to build up in the atmosphere.But in their study Berkeley laboratory test experts Reilly, Arasteh and Rubin revealed something truly remarkable when setting out to apply those assumed properties of carbon dioxide – enshrined in climate change theory – to create better performing insulated double-glazing window manufacture.What was discovered was that under stringent lab conditions it can be shown that regular air delays/traps heat better than greenhouse gases such as CO2!This important empirical data shows the opposite of one of the key axioms of consensus climate science theory: that carbon dioxide traps heat and/or delays cooling in the atmosphere. Instead, the Berkeley scientists’ rigorous tests designed to exploit a supposed known feature of ‘greenhouse gases’ actually discredits the very cornerstone of the accepted science of ‘greenhouse gas theory’ and man-made global warming.THE BERKELEY LAB EXPERIMENTWhat the scientists did: They took ‘greenhouse gases’ (SF6, CO2, NH3, and N2O) and some other gasses, put them between panes of glass and tested and measured their abilities to trap heat and/or inhibit heat loss.Or, in more technical terms they tested, “the existing heat transfer model of multipane windows filled with gasses to include the effects of infrared absorption within the gasses.”Berkeley’s lab experts Reilly, Arasteh and Rubin meticulously applied “a one-dimensional, finite-element, control-volume approach for calculating the heat transfer across a horizontal window filled with an infrared absorbing gas.”If greenhouse gas theory is true and not just the computer modelers’ musings then what would be apparent would be “gas-fills for such windows [that] should have a low thermal conductivity and a high kinematic viscosity.”Crucially, Reilly, Arasteh and Rubin ensured they tested for the coupled effects of conduction and radiation (not convection because climate science isn’t concerned with convection). What the techie trio turned up was an extensive body of experimental data on the heat transfer rates through windows filled with infrared absorbing gasses and heated from above (to minimize that unwanted convection).After exhaustive experiments Berkeley’s brightest and best reported that “the effect of the infrared radiation properties of CO2 is unnoticeable.” And that infrared absorbing gasses “are not as effective as low-emittance coatings for reducing radiative heat transfer.”In effect, the results for CO2 being a good trapper of heat/delayer of heat loss, showed a big fat zero. And that’s why you don’t see double glazing manufacturers eager to fill the voids between the glass panes of their windows with carbon dioxide.WHEN THE FACTS DON’T FIT THE THEORYBut this discovery isn’t ‘new.’ Reilly, Arasteh and Rubin conducted this important work at the Applied Science Division, Lawrence Berkeley Laboratory, Berkeley, California in 1989. Once again it provides another example of the wilful negligence of a powerful clique of government ‘scientists’ unwilling or incapable of digesting hard-won applied scientific knowledge.By contrast, engineers and practitioners from the ‘hard’ sciences have long known that carbon dioxide only serves as a coolant in industry applications (e.g. with dry ice, pre- CFC era refrigeration). There is no known industrial application where carbon dioxide operates to trap heat or delay cooling.But academia is a closed shop to applied sciences – it is a cloistered world of bookishness, pal review and mutual self-interest geared to winning their slice of lucrative government ‘research’ grants.As in much of the ‘soft’ sciences practiced in academia there is little or no need to know two cents about how the real world works. “Who needs a PhD in Physics or Chemistry to do climate science when computer models are ‘right’ and the science is ‘settled’?” bemoans retired Analytical Chemist, Hans Schreuder (Principia Scientific International).But it gets worse.Contrary to consensus science beliefs carbon dioxide wasn’t so much ‘trapping’ or delaying heat in the system, it was very effectively losing it – and the wider the gap in the double-glazed panes the more the CO2 gas filler showed U-value energy loss (see graph below).So much so, the Berkeley lab results proved that “the gas, however, emits infrared radiation thus degrading the performance of the SF6-filled window.” In other words, putting a ‘greenhouse gas’ into double-glazing does the opposite of what double-glazed windows are supposed to do: retain/retard heat loss.Indeed, the Berkeley Laboratory tests proved that:“Not only do the absorbing gasses generally have low kinematic viscosities, but the infrared emission from the gas adversely affects the window http://performance….in fact, air outperforms SF6 [Sulfur hexafluoride – a greenhouse gas] at gap widths greater than 9 mm in a vertical window and the benefits from infrared absorption by SF6 have been negated by the magnitude of the convection.”The Berkeley trio prove “Not only do the absorbing gasses generally have low kinematic viscosities, but the infrared emission from the gas adversely affects the window performance.” This study showed that, “For small vertical gap widths and for windows heated from above, where convection is negligible, our model agrees well with experimental data. For larger vertical gap widths, where energy savings from the use of infrared absorbing gasses may begin to accrue, convection effects will begin to take effect and negate the positive impact of going to larger gap widths.”In other words, even the every-day ‘normal’ air we breathe delays/traps heat better than greenhouse gases such as CO2! And when the effect of convection (wind to you and me) is added to the thermal mix, cooling predominates.Thus, whereby cooling in the atmosphere occurs by a mixture of radiation, conduction and convection it is convection (heat loss by movement of air) that is king; so pervasive and dominant is convection that heat transfer by radiation and conduction are easily overwhelmed by it in a gaseous environment (such as earth’s open atmosphere).These facts are in line with those evidenced in 2011 in the ground-breaking work performed by Professor Nasif Nahle, Monterrey, Mexico [2]. Nahle showed that by application of standard gas equations any “trapping” effect by CO2 could last not a moment longer than a miniscule five milliseconds – that’s quicker than the blink of an eye to all you non-scientists.Industry experts with PhD’s in thermodynamics have long been saying that CO2 is shown to do the opposite of what government-funded academics say it does. Even renowned experts like Dick Topping Director of Appliance Research (TIAX, LLC) are routinely ignored. Topping writes: “The use of CO2 as a refrigerant dates back more than a century, but it fell out of favor in the air-conditioning and refrigeration industry with the development of chlorofluorocarbons (CFCs) in the 1930s.” [3]And as recently as 2009 applied scientists in Japan were showing how money is to be made exploiting CO2’s proven cooling properties. There Sanyo developed that country’s first commercially-viable CO2 refrigerant which they say (ironically) could “greatly contribute to the prevention of global warming.”[4]In fact, nowhere will you find alarmist academics showing you a practical use of carbon dioxide as a heat-trapping agent.But do we think the climate ‘experts’ in universities (paid to promote climate alarm over CO2 emissions) are soon going to admit their errors – will they ever bite the grant-giving government hand that feeds them and admit to such real-world truths? No chance.[1] MAS. Reilly, D. Arasteh, and M. Rubin, ‘The Effects of Infrared Absorbing Gasses on Window Heat Transfer: A Comparison of Theory and Experiment,’ Applied Science Division, Lawrence Berkeley Laboratory, Berkeley, California 94720; Published in Solar Energy Materials 20 (1990) pp. 277-288, North Holland, Elsevier Science Publishers B.V. The Effects of Infrared Absorbing Gasses on Window heat Transfer: A Comparison of Theory and Experiment[2] Nahle, N. S., Determination of the Total Emissivity of a Mixture of Gases Containing 5% of Water Vapor and 0.039% of Carbon Dioxide at Overlapping Absorption Bands (2011), Scientific Research Division, Biology Cabinet Mexico.[3] Topping R., Carbon Dioxide Refrigerant Makes a Comeback (2004) Design News (accessed online: September 24, 2012)[4] Sanyo Develops Japan’s First Co2 Refrigerant Direct Expansion Type Refrigeration System, http://www.gea-consulting.com (accessed online: September 24, 2012)

HERE ARE A FEW!REALISM is the philosophy that seeks to explain what actually happens. It’e principle representative is Aristotle. Other notable Realists are Socrates, Plato, Cicero, Boethius, Augustine, Albertus Magnus, Aquinas, Bonaventure, Dun Scotus, Cajetan, Anselm, Gilbert de la Porrée, Peter Abelard, Roger Bacon, William of Ockham, Jean Buridan, Luigi Taparelli ; the Jewish philosophers Moses Maimonides and Gersonides; and the Muslim philosophers, Avicenna, Algazel,, and Averroes. The medieval tradition of scholasticism continued to flourish as late as the 17th century, in figures such as Francisco Suárez and John of St. Thomas. More recently we see the Dominican Order producing Thomistic Realism as in Reginald Garrigou-Lagrange, Tommaso Maria Zigliara, Juan González Arintero ; laymen are Etienne Gilson, Mortimer Adler, Charles De Koninck, Wolfgang Smith, Ron McArthur, Marc & Richard Berquist, John Neumeyer, and the contemporary blogger Edward Feser.Aesthetic Realism, was founded in 1941 by the American poet and critic Eli Siegel (1902–1978). He defined it as a three-part study: “One, Man's greatest, deepest desire is to like the world honestly. Two, The one way to like the world honestly, not as a conquest of one's own, is to see the world as the aesthetic oneness of opposites. Three, The greatest danger or temptation of man is to get a false importance or glory from the lessening of things not himself; which lessening is Contempt. Even more briefly, these three divisions can be described as: One, Liking the world; Two, The opposites; Three, The meaning of contempt.” Aesthetic Realism - WikipediaCalvinism (also called the Reformed tradition, Reformed Christianity, Reformed Protestantism, or the Reformed faith) is a major branch of Protestantism that follows the theological tradition and forms of Christian practice set down by John Calvin and other Reformation-era theologians. The namesake of the movement, French reformer John Calvin, renounced Roman Catholicism and embraced Protestant views in the late 1520s or early 1530s, as the earliest notions of later Reformed tradition were already espoused by Huldrych Zwingli. The movement was first called Calvinism, referring to John Calvin, by Lutherans who opposed it. Many within the tradition find it either an indescriptive or an inappropriate term and would prefer the word Reformed to be used instead.The most important Reformed theologians include Calvin, Zwingli, Martin Bucer, William Farel, Heinrich Bullinger, Peter Martyr Vermigli, Theodore Beza, and John Knox. In the twentieth century, Abraham Kuyper, Herman Bavinck, B. B. Warfield, J. Gresham Machen, Karl Barth, Martyn Lloyd-Jones, Cornelius Van Til, Gordon Clark, and R. C. Sproul were influential. Contemporary Reformed theologians include J. I. Packer, John MacArthur, Timothy J. Keller, David Wells, and Michael Horton. Calvinism - WikipediaCapitalism is an economic system based on the private ownership of the means of production and their operation for profit.Characteristics central to capitalism include private property, capital accumulation, wage labor, voluntary exchange, a price system and competitive markets.In a capitalist market economy, decision-making and investments are determined by every owner of wealth, property or production ability in financial and capital markets, whereas prices and the distribution of goods and services are mainly determined by competition in goods and services markets. Capitalism - WikipediaAnalytic philosophy (sometimes analytical philosophy) is a style of philosophy that became dominant in the Western world at the beginning of the 20th century. The term can refer to one of several things:As a philosophical practice, it is characterized by an emphasis on argumentative clarity and precision, often making use of formal logic, conceptual analysis, and, to a lesser degree, mathematics and the natural sciences.As a historical development, analytic philosophy refers to certain developments in early 20th-century philosophy that were the historical antecedents of the current practice. Central figures in this historical development are Bertrand Russell, Ludwig Wittgenstein, G.E. Moore, Gottlob Frege, and the logical positivists. In this more specific sense, analytic philosophy is identified with specific philosophical traits (many of which are rejected by many contemporary analytic philosophers), such as:The logical-positivist principle that there are not any specifically philosophical facts and that the object of philosophy is the logical clarification of thoughts. This may be contrasted with the traditional foundationalism, which considers philosophy to be a special science (i.e., the discipline of knowledge) that investigates the fundamental reasons and principles of everything.Consequently, many analytic philosophers have considered their inquiries as continuous with, or subordinate to, those of the natural sciences. This is an attitude that begins with John Locke, who described his work as that of an "underlabourer" to the achievements of natural scientists such as Newton. During the 20th century, the most influential advocate of the continuity of philosophy with science was Willard Van Orman Quine. The principle that the logical clarification of thoughts can be achieved only by analysis of the logical form of philosophical propositions. The logical form of a proposition is a way of representing it (often using the formal grammar and symbolism of a logical system), to reduce it to simpler components if necessary, and to display its similarity with all other propositions of the same type. However, analytic philosophers disagree widely about the correct logical form of ordinary language. The neglect of generalized philosophical systems in favor of more restricted inquiries stated rigorously, or ordinary language.According to a characteristic paragraph by Russell:Modern analytical empiricism [...] differs from that of Locke, Berkeley, and Hume by its incorporation of mathematics and its development of a powerful logical technique. It is thus able, in regard to certain problems, to achieve definite answers, which have the quality of science rather than of philosophy. It has the advantage, in comparison with the philosophies of the system-builders, of being able to tackle its problems one at a time, instead of having to invent at one stroke a block theory of the whole universe. Its methods, in this respect, resemble those of science.[A HISTORY OF WESTERN PHILOSOPHY by Bertrand RussellIn the United Kingdom, United States, Canada, Australia, New Zealand and Scandinavia, the majority of university philosophy departments today identify themselves as "analytic" departments. Analytic philosophy is often understood in contrast to other philosophical traditions, most notably continental philosophies such as existentialism and phenomenology, and also Thomism and Marxism. Analytic philosophy - WikipediaContinental philosophy is a set of 19th- and 20th-century philosophical traditions from mainland Europe.This sense of the term originated among English-speaking philosophers in the second half of the 20th century, who used it to refer to a range of thinkers and traditions outside the analytic movement. Continental philosophy includes German idealism, phenomenology, existentialism (and its antecedents, such as the thought of Kierkegaard and Nietzsche), hermeneutics, structuralism, post-structuralism, deconstruction, French feminism, psychoanalytic theory, and the critical theory of the Frankfurt School and related branches of Western Marxism.First, continental philosophers generally reject the view that the natural sciences are the only or most accurate way of understanding natural phenomena. This contrasts with many analytic philosophers who consider their inquiries as continuous with, or subordinate to, those of the natural sciences. Continental philosophers often argue that science depends upon a "pre-theoretical substrate of experience" (a version of Kantian conditions of possible experience or the phenomenological "lifeworld") and that scientific methods are inadequate to fully understand such conditions of intelligibility.Second, continental philosophy usually considers these conditions of possible experience as variable: determined at least partly by factors such as context, space and time, language, culture, or history. Thus continental philosophy tends toward historicism (or historicity). Where analytic philosophy tends to treat philosophy in terms of discrete problems, capable of being analyzed apart from their historical origins (much as scientists consider the history of science inessential to scientific inquiry), continental philosophy typically suggests that "philosophical argument cannot be divorced from the textual and contextual conditions of its historical emergence".Third, continental philosophy typically holds that human agency can change these conditions of possible experience: "if human experience is a contingent creation, then it can be recreated in other ways".[8] Thus continental philosophers tend to take a strong interest in the unity of theory and practice, and often see their philosophical inquiries as closely related to personal, moral, or political transformation. This tendency is very clear in the Marxist tradition ("philosophers have only interpreted the world, in various ways; the point, however, is to change it"), but is also central in existentialism and post-structuralism.A final characteristic trait of continental philosophy is an emphasis on metaphilosophy. In the wake of the development and success of the natural sciences, continental philosophers have often sought to redefine the method and nature of philosophy.[9] In some cases (such as German idealism or phenomenology), this manifests as a renovation of the traditional view that philosophy is the first, foundational, a priori science. In other cases (such as hermeneutics, critical theory, or structuralism), it is held that philosophy investigates a domain that is irreducibly cultural or practical. And some continental philosophers (such as Kierkegaard, Nietzsche, the later Heidegger, or Derrida) doubt whether any conception of philosophy can coherently achieve its stated goals.Ultimately, the foregoing themes derive from a broadly Kantian thesis that knowledge, experience, and reality are bound and shaped by conditions best understood through philosophical reflection rather than exclusively empirical inquiry.The term continental philosophy, in the above sense, was first widely used by English-speaking philosophers to describe university courses in the 1970s, emerging as a collective name for the philosophies then widespread in France and Germany, such as phenomenology, existentialism, structuralism, and post-structuralism. However, the term (and its approximate sense) can be found at least as early as 1840, in John Stuart Mill's 1840 essay on Coleridge, where Mill contrasts the Kantian-influenced thought of "Continental philosophy" and "Continental philosophers" with the English empiricism of Bentham and the 18th century generally. This notion gained prominence in the early 20th century as figures such as Bertrand Russell and G. E. Moore advanced a vision of philosophy closely allied with natural science, progressing through logical analysis. This tradition, which has come to be known broadly as "analytic philosophy", became dominant in Britain and the United States from roughly 1930 onward. Russell and Moore made a dismissal of Hegelianism and its philosophical relatives a distinctive part of their new movement. Commenting on the history of the distinction in 1945, Russell distinguished "two schools of philosophy, which may be broadly distinguished as the Continental and the British respectively", a division he saw as operative "from the time of Locke". Since the 1970s, however, many philosophers in the United States and Britain have taken interest in continental philosophers since Kant, and the philosophical traditions in many European countries have similarly incorporated many aspects of the "analytic" movement. Self-described analytic philosophy flourishes in France, including philosophers such as Jules Vuillemin, Vincent Descombes, Gilles Gaston Granger, François Recanati, and Pascal Engel. Likewise, self-described "continental philosophers" can be found in philosophy departments in the United Kingdom, North America, and Australia, and some well-known analytic philosophers claim to conduct better scholarship on continental philosophy than self-identified programs in continental philosophy, particularly at the level of graduate education. "Continental philosophy" is thus defined in terms of a family of philosophical traditions and influences rather than a geographic distinction. The issue of geographical specificity has been raised again more recently in post-colonial and decolonial approaches to "continental philosophy", which critically examine the ways that European imperial and colonial projects have influenced academic knowledge production. For this reason, some scholars have advocated for "post-continental philosophy" as an outgrowth of continental philosophy. Continental philosophy - WikipediaChristianity and Hellenistic philosophies experienced complex interactions during the first to the fourth centuries.As Christianity spread throughout the Hellenic world, an increasing number of church leaders were educated in Greek philosophy. The dominant philosophical traditions of the Greco-Roman world then were Stoicism, Platonism, and Epicureanism. Stoicism and, particularly, Platonism were readily incorporated into Christian ethics and Christian theology.Christian assimilation of Hellenic philosophy was anticipated by Philo and other Greek-speaking Alexandrian Jews. Philo's blend of Judaism, Platonism, and Stoicism strongly influenced Christian Alexandrian writers like Origen and Clement of Alexandria, as well as, in the Latin world, Ambrose of Milan.One early Christian writer of the 2nd and early 3rd century, Clement of Alexandria, demonstrated Greek thought in writing,"Philosophy has been given to the Greeks as their own kind of Covenant, their foundation for the philosophy of Christ ... the philosophy of the Greeks ... contains the basic elements of that genuine and perfect knowledge which is higher than human ... even upon those spiritual objects." (Miscellanies 6. 8)The Church historian Eusebius suggested, essentially, in his preparation for the Gospel that Greek philosophy, although in his view derivative, was concordant with Hebrew notions. Augustine of Hippo, who ultimately systematized Christian philosophy, wrote in the 4th and early 5th century,But when I read those books of the Platonists I was taught by them to seek incorporeal truth, so I saw your 'invisible things, understood by the things that are made' (Confessions 7. 20).John Burnet (1892) notedThe Neoplatonists were quite justified in regarding themselves as the spiritual heirs of Pythagoras; and, in their hands, philosophy ceased to exist as such, and became theology. And this tendency was at work all along; hardly a single Greek philosopher was wholly uninfluenced by it. In later days, Apollonios of Tyana showed in practice what this sort of thing must ultimately lead to. The theurgy and thaumaturgy of the late Greek schools were only the fruit of the seed sown by the generation which immediately preceded the Persian War. Christianity and Hellenistic philosophy - WikipediaCompatibilism is the belief that free will and determinism are mutually compatible and that it is possible to believe in both without being logically inconsistent. Compatibilists believe freedom can be present or absent in situations for reasons that have nothing to do with metaphysics. They say causal determinism does not exclude the truth of possible future outcomes.Similarly, political liberty is a non-metaphysical concept. Statements of political liberty, such as the United States Bill of Rights, assume moral liberty: the ability to choose to do otherwise than one does. Compatibilism - Wikipedia [THIS IS VERY POPULAR AMONG THE YOU TUBE SET.]Existentialism (/ˌɛɡzɪˈstɛnʃəlɪzəm/) is a tradition of philosophical enquiry which takes as its starting point the experience of the human subject—not merely the thinking subject, but the acting, feeling, living human individual. It is associated mainly with certain 19th- and 20th-century European philosophers who, despite profound doctrinal differences, shared the belief in that beginning of philosophical thinking.While the predominant value of existentialist thought is commonly acknowledged to be freedom, its primary virtue is authenticity. In the view of the existentialist, the individual's starting point is characterized by what has been called "the existential angst" (or variably, existential attitude, dread, etc.), or a sense of disorientation, confusion, or dread in the face of an apparently meaningless or absurd world. Many existentialists have also regarded traditional systematic or academic philosophies, in both style and content, as too abstract and remote from concrete human experience.Søren Kierkegaard is generally considered to have been the first existentialist philosopher, though he did not use the term existentialism. He proposed that each individual—not society or religion—is solely responsible for giving meaning to life and living it passionately and sincerely, or "authentically".Existentialism became popular in the years following World War II, thanks to Jean-Paul Sartre, who read Martin Heidegger while in a POW camp, and strongly influenced many disciplines besides philosophy, including theology, drama, art, literature, and psychology. Existentialism - WikipediaMarxism is a method of socioeconomic analysis that views class relations and social conflict using a materialist interpretation of historical development and takes a dialectical view of social transformation. It originates from the works of 19th-century German philosophers Karl Marx and Friedrich Engels. Marxism has developed into many different branches and schools of thought, with the result that there is now no single definitive Marxist theory.Different Marxian schools place a greater emphasis on certain aspects of classical Marxism while rejecting or modifying other aspects. Many schools of thought have sought to combine Marxian concepts and non-Marxian concepts which has then led to contradictory conclusions. It has been argued that there is a movement toward the recognition that historical materialism and dialectical materialism remains the fundamental aspect of all Marxist schools of thought. This view is refuted by some post-Marxists such as Ernesto Laclau and Chantal Mouffe, who claim that history is not only determined by the mode of production, but also by consciousness and will.Marxism has had a profound impact on global academia and has influenced many fields such as archaeology, anthropology, media studies, science studies, political science, theater, history, sociology, art history and theory, cultural studies, education, economics, ethics, criminology, geography, literary criticism, aesthetics, film theory, critical psychology and philosophy. Marxism - WikipediaMaterialism is a form of philosophical monism that holds that matter is the fundamental substance in nature, and that all things, including mental states and consciousness, are results of material interactions. According to philosophical materialism, mind and consciousness are by-products or epiphenomena of material processes (such as the biochemistry of the human brain and nervous system), without which they cannot exist. This concept directly contrasts with idealism, where mind and consciousness are first-order realities to which matter is subject and material interactions are secondary.Materialism is closely related to physicalism—the view that all that exists is ultimately physical. Philosophical physicalism has evolved from materialism with the theories of the physical sciences to incorporate more sophisticated notions of physicality than mere ordinary matter (e.g. spacetime, physical energies and forces, and dark matter). Thus the term physicalism is preferred over materialism by some, while others use the terms as if they are synonymous.Philosophies contradictory to materialism or physicalism include idealism, pluralism, dualism, and other forms of monism. Materialism - WikipediaProgressivism is the support for or advocacy of social reform. As a philosophy, it is based on the idea of progress, which asserts that advancements in science, technology, economic development and social organization are vital to the improvement of the human condition. Progressivism - WikipediaScientism is the promotion of science as the best or only objective means by which society should determine normative and epistemological values. The term scientism is generally used critically, implying a cosmetic application of science in unwarranted situations considered not amenable to application of the scientific method or similar scientific standards. Scientism - WikipediaSecularism, as defined in the Merriam-Webster dictionary, is the "indifference to, or rejection or exclusion of, religion and religious considerations". In certain context, the word can refer to anticlericalism, atheism, desire to exclude religion from social activities or civic affairs, banishment of religious symbols from the public sphere, state neutrality toward religion, the separation of religion from state, or disestablishment (separation of church and state).As a philosophy, secularism seeks to interpret life on principles taken solely from the material world, without recourse to religion. Secularism draws its intellectual roots from Greek and Roman philosophers such as Zeno of Citium and Marcus Aurelius; from Enlightenment thinkers such as John Locke, Denis Diderot, Voltaire, Baruch Spinoza, James Madison, Thomas Jefferson, and Thomas Paine; and from more recent freethinkers atheists such as Matthew W. Dillahunty, Robert Ingersoll, Bertrand Russell, and Christopher Hitchens. It shifts the focus from religion to other "temporal" and "this-worldly" things, with emphasis on nature, reason, science, and development. In political terms, secularism is the principle of the separation of government institutions and persons mandated to represent the state from religious institution and religious dignitaries (the attainment of such is termed secularity). Defined briefly, secularism means that governments should remain neutral on the matter of religion and should not enforce nor prohibit the free exercise of religion, leaving religious choice to the liberty of the people. One form of secularism is asserting the right to be free from religious rule and teachings, or, in a state declared to be neutral on matters of belief, from the imposition by government of religion or religious practices upon its people. Another form of secularism is the view that public activities and decisions, especially political ones, should be uninfluenced by religious beliefs or practices.There exist distinct traditions of secularism in the West (e.g., French and Anglo-American) and beyond (e.g., in India). The purposes and arguments in support of secularism vary widely. In European laicism, it has been argued that secularism is a movement toward modernization, and away from traditional religious values (also known as secularization). This type of secularism, on a social or philosophical level, has often occurred while maintaining an official state church or other state support of religion. In the United States, some argue that state secularism has served to a greater extent to protect religion and the religious from governmental interference, while secularism on a social level is less prevalent.On the other hand, Meiji era Japan maintained that it was secular and allowed freedom of religion despite enforcing State Shinto and continuing to prohibit certain "superstitions;" scholar of religion Jason Ānanda Josephson has labelled this conception of the secular "the Shinto Secular" and noted that it follows a pattern established in certain European constitutions. Secularism - WikipediaSocialism is a range of economic and social systems characterised by social ownership of the means of production and workers' self-management as well as the political theories and movements associated with them. Social ownership can be public, collective or cooperative ownership, or citizen ownership of equity. There are many varieties of socialism and there is no single definition encapsulating all of them, with social ownership being the common element shared by its various forms.Socialist systems are divided into non-market and market forms. Non-market socialism involves replacing factor markets and money with engineering and technical criteria based on calculation performed in-kind, thereby producing an economic mechanism that functions according to different economic laws from those of capitalism. Non-market socialism aims to circumvent the inefficiencies and crises traditionally associated with capital accumulation and the profit system. By contrast, market socialism retains the use of monetary prices, factor markets and in some cases the profit motive, with respect to the operation of socially owned enterprises and the allocation of capital goods between them. Profits generated by these firms would be controlled directly by the workforce of each firm, or accrue to society at large in the form of a social dividend.The socialist calculation debate, originated by the economic calculation problem, concerns the feasibility and methods of resource allocation for a socialist system. Socialism - WikipediaReligious humanism is an integration of humanist ethical philosophy with congregational but non-theistic rituals and community activity which center on human needs, interests, and abilities. Self-described religious humanists differ from secular humanists mainly in that they regard the humanist life stance as their religion and organise using a congregational model. Religious humanism is a classic example of a nontheistic religion.Religious humanists typically organise in the 21st century under the umbrella of Ethical Culture or Ethical Humanism. It remains largely a United States phenomenon; a British ethical culture movement was briefly highly active in the late 19th and early 20th centuries, but by the 1960s had largely abandoned its "religious" trappings, and asserted humanism less as a religious identity and more as a useful label to describe rational and non-religious attitudes to morality and ethics. Ethical Culture and religious humanism groups first formed in the United States from Unitarian ministers who, not believing in god, sought to build a secular religion influenced on the thinking of French philosopher Auguste Comte. Religious humanism - WikipediaIn sociology, anthropology, and linguistics, structuralism is the methodology that implies elements of human culture must be understood by way of their relationship to a broader, overarching system or structure. It works to uncover the structures that underlie all the things that humans do, think, perceive, and feel. Alternatively, as summarized by philosopher Simon Blackburn, structuralism is "the belief that phenomena of human life are not intelligible except through their interrelations. These relations constitute a structure, and behind local variations in the surface phenomena there are constant laws of abstract structure". Structuralism in Europe developed in the early 1900s, mainly in France and Russian Empire, in the structural linguistics of Ferdinand de Saussure and the subsequent Prague, Moscow and Copenhagen schools of linguistics. In the late 1950s and early 1960s, when structural linguistics were facing serious challenges from the likes of Noam Chomsky and thus fading in importance, an array of scholars in the humanities borrowed Saussure's concepts for use in their respective fields of study. French anthropologist Claude Lévi-Strauss was arguably the first such scholar, sparking a widespread interest in structuralism. Structuralism - WikipediaUtilitarianism is a family of consequentialist ethical theories that promotes actions that maximize happiness and well-being for the affected individuals. Although different varieties of utilitarianism admit different characterizations, the basic idea behind all of them is to in some sense maximize utility, which is often defined in terms of well-being or related concepts. For instance, Jeremy Bentham, the founder of utilitarianism, described utility as "that property in any object, whereby it tends to produce benefit, advantage, pleasure, good, or happiness...[or] to prevent the happening of mischief, pain, evil, or unhappiness to the party whose interest is considered." Utilitarianism is a version of consequentialism, which states that the consequences of any action are the only standard of right and wrong. Unlike other forms of consequentialism, such as egoism and altruism, utilitarianism considers the interests of all humans equally.Proponents of utilitarianism have disagreed on a number of points, such as whether actions should be chosen based on their likely results (act utilitarianism) or whether agents should conform to rules that maximize utility (rule utilitarianism). There is also disagreement as to whether total (total utilitarianism), average (average utilitarianism) or minimum utility should be maximized.Though the seeds of the theory can be found in the hedonists Aristippus and Epicurus, who viewed happiness as the only good, the tradition of utilitarianism properly began with Bentham, and has included John Stuart Mill, Henry Sidgwick, R. M. Hare, David Braybrooke, and Peter Singer. It has been applied to social welfare economics, the crisis of global poverty, the ethics of raising animals for food and the importance of avoiding existential risks to humanity. Utilitarianism - WikipediaValue theory involves various approaches that examine how, why, and to what degree humans value things and whether the object or subject of valuing is a person, idea, object, or anything else.Within philosophy, it can be known as ethics or axiology. Early philosophical investigations sought to understand good and evil and the concept of "the good". Today, much of value theory aspires to the scientifically empirical, recording what people do value and attempting to understand why they value it in the context of psychology, sociology, and economics. In ecological economics value theory is separated into two types: donor-type value and receiver-type value. Ecological economists tend to believe that 'real wealth' needs a donor-determined value as a measure of what things were needed to make an item or generate a service (H. T. Odum, Environmental Accounting: Emergy and environmental decision-making, 1996).In other fields, theories positing the importance of values as an analytical independent variable (including those put forward by Max Weber, Émile Durkheim, Talcott Parsons, and Jürgen Habermas). Classical examples of sociological traditions which deny or downplay the question of values are institutionalism, historical materialism (including Marxism), behaviorism, pragmatic-oriented theories, postmodern philosophy and various objectivist-oriented theories.At the general level, there is a difference between moral and natural goods. Moral goods are those that have to do with the conduct of persons, usually leading to praise or blame. Natural goods, on the other hand, have to do with objects, not persons. For example, the statement "Mary is a good person" uses 'good' very differently than in the statement "That is good food".Ethics is mainly focused on moral goods rather than natural goods, while economics has a concern in what is economically good for the society but not an individual person and is also interested in natural goods. However, both moral and natural goods are equally relevant to goodness and value theory, which is more general in scope. Value theory - WikipediaAnd these are just a few!