Hierarchical Vhdl Designs: Fill & Download for Free

Not exactly free ($169/year) but ViaDesigner is very capable mixed-signal circuit design and simulation environment that includes:Schematic Capture (multi-page & hierarchical)VHDL Digital DesignVerilog Digital DesignSPICE ModelingVHDL-AMS High-Level Mixed-Signal ModelingAll of these design entry methods can be combined in a unified simulation environment.(I do work for the company that makes ViaDesigner and yes I'm in marketing but I have designed chips and I like using ViaDesigner)NASA has publicly announced that they use ViaDesigner, NASA - Space Exploration and Higher Education Will Both Benefit From New Partnership with NASA, Industry, and HBCU Communities.

Very High Speed Integrated Circuit (VHSIC) Developed by the department of defense (1981) and rights where given to IEEE in 1986 became a standard and published in 1987.Standard language used to describe digital hardware devices, systems and componentsRevised standard published in 1993 (VHDL 1076-1993) regulated by VHDL international (VI)VHDL References:IEEE Standard VHDL Language Reference Manual (1076 –1993) (1076-2002)“RTL Hardware Design using VHDL –Coding for Efficiency, Portability, and Scalability”by Pong P. Chu, Wiley-InterScience, 2006“Introductory VHDLFrom Simulation to Synthesisby SudhakarYalamanchilli, 2002, Xilinx Design Series, Prentice Hall“VHDL Made Easy”by David Pellerinand Douglas Taylor, 1997, Prentice HallVHDL Uses top-down approach to partition design into small blocks ‘components’–Entity: describes interface signals & basic building blocks–Architecture: describes behavior, each entity can have multiple Architectures–Configuration: sort of parts list for a design, which behavior to use for each entity.–Package: toolbox used to build designVerilog was developed by Gateway Design Automation (1980), later acquired by Cadence Design(1989) who made it public in 1990. It had became a standardized in 1995 by IEEE (Std 1364) regulated by Open Verilog International (OVI)Verilog only has one building block so called Module: modules connect through their port similarly as in VHDL, there is only one module per file.–A top level invokes instances of other modules.–Modules can be specified behaviorally or structurally.•Behavioral specification defines behavior of digital system•Structural specification defines hierarchical interconnection of sub modulesThere are not many differences as to the capabilities of VHDL vs Verilog. The choice of which one to use is often based in personal preference & other issues such as availability of tools & commercial terms.•VHDL is “harder” to learn ADA or Pascal like.•Verilog is “easier” to learn C-like.According to Gary Smith, EDA Analyst at Dataquest, he says that although Verilog is dominating the marketVHDL is a strongly typed language, and scripts that are not strongly typed, are unable to compile. It does not allow the intermixing, or operation of variables, withdifferent classes.Verilog uses weak typing, which is the opposite of a strongly typed language.Another difference is the case sensitivity. Verilog is case sensitive, and would not recognize a variable if the case used is not consistent with what it was previously. On the other hand, VHDL is notcase sensitive, and users can freely change the case, as long as the characters in the name, and theorder, stay the sameIn general, Verilog is easier to learn than VHDL. This is due, in part, to the popularity of the C programming language and later C++. There are standard conventions programmers learn and become familiar with Verilog. VHDL is a little bit more difficult to learn and program.VHDL has the advantage of having a lot more constructs that aid in high-level modeling.Sample VHDL Codereg1: process (rst, clk)  begin  if rst = '1' then  q_reg <= (others => '0');  q_i <= (others => '0');  elsif rising_edge(clk) then  if s_l = '1' then  q_i(0) <= q_i(7);  loop1: for i in 6 downto 0 loop  q_i(i + 1) <= q_i(i);  end loop loop1;  q_reg <= y;  else  q_i <= q_reg;  q_reg <= y;  end if;  end if;  end process reg1; Sample Verilog Codealways @(posedge CLK or posedge RST) begin  if (RST) begin  q_reg = 0;   Q = 0;   end else if (S_L) begin  Q[7:0] = {Q[6:0],Q[7]};   q_reg = Y;  end else begin  Q = q_reg;   q_reg = Y;   end end Complex data types and packagesare very desirable when programming big and complex systems, that might have a lot of functional parts. Verilog has no concept of packages, and all programming must be done with the simple datatypes that are provided by the programmer. Lastly, Verilog lacks the library management of software programming languages. This means that Verilog will not allow programmers to put needed modules in separate files that are called during compilation. Large projects on Verilog might end up in a large, and difficult to trace the file. In Verilog, the language is more compact, as the Verilog language is more of a hardware modeling language. You will end up typing few lines of code and it draws similarities to the C language. Verilog has a better grasp on hardware modeling, but has a lower level of programming constructs.Looking at this example code, we can compare at the how a MUX can be programmed through VHDL and Verilog.The layout of these programs are very similar; you can reasonably follow what each version of the code is doing. The VHDL version is longer then the Verilog, but it can be understood better.

Similarities:1) Build automation. You need this to manage different versions of your IC designs and software builds. Git, Mercurial, Subversion, and CVS can be used for this. They are free.2) Test automation. Automated regression testing for software and automated regression verification for ICs help ensure that the latest additions/modifications to the design does not cause previously implemented modules/subcircuits to fail. Automated debuggers also exist for software and digital ICs.3) System or high-level design. UML can be used for both. You can use models of computation for design ICs or software at the system-level of abstraction or for architectural design (digital VLSI architecture, RF system architecture, and software architecture). System-level design languages (such as SystemC and SystemC-AMS) can be used for specifying software and/or ICs at the system level, and to facilitate design space exploration. Tools exist for software refactoring and digital VLSI refactoring.4) Formal methods and verification. Just as you can use design by contract or contract programming for software development, you can use assertions for specifying the requirements for the IC. There also exists formal methods and verification techniques for analog and mixed-signal circuits. They are not very well-developed, but they do exist.5) Process control. Techniques and methodologies based Six Sigma and design for experiments can be used for process improvement.6) Iterative and Incremental development (IDD). Many software projects use software development processes that support IDD, since software project requirements can change rapidly over the cost of the project. Since IC design is becoming more software-like, see aforementioned point on SystemC and SystemC-AMS, you want to iterate the design cycle several times till you meet your design objectives and constraints (pass beta testing for software or arrive at design closure for ICs).7) Fault isolation and fault-tolerant design. The same concepts are used for software design and IC design.8) Architectural design (hierarchical and modular design) for software and ICs (especially VLSI systems) are the same, or are similar9) Algorithm design and analysis (including computational complexity and circuit complexity with applications to logic circuits). VLSI implementation of sorting, computer vision, and video/image/signal processing algorithms requires algorithm design at TLM (transaction-level model) and RTL (register-transfer level). Circuit complexity of digital VLSI systems should be reduced.10) Automated document generation (via documentation generators for C++, SystemC, Verilog/VHDL, MATLAB, and Perl/Tcl/Python)Differences.1) Testing. The way you test software and ICs are different. You can test software on a computer, but you need expensive automated test equipment for ICs.2) Verification. IC verification involves simulation and formal verification, while software verification typically only refers to software formal verification (some people may include software profiling and software timing analysis - as in WCET analysis).3) Software implementation involves programming at a single level of abstraction... Either a set of high-level languages, such as C++ and Python, or assembly language. You compile/assemble that to produce a working binary (executable file)... You can mix programming languages/paradigms, but you usually don't want to move between levels of abstraction (from a modeling language such as UML to high-level code and then to assembly code and finally to binary/machine code).IC design involves working at different levels of abstraction. For analog circuits and mixed-signal, you need to implement the architectural design with transistor-level circuits, before you can move on to physical design (producing the layout). Subsequently, you need to produce the masks for the design so that the design can be manufactured.For digital IC design, you need to implement the circuits at the behavioral level, followed by the logic level. Subsequently, you need to implement the circuit at the physical level (i.e., layout) and then produce the masks.Therefore, IC design is much more complicated in terms of the number of required steps than software development.4) Digital ICs (and analog and mixed-signal circuits) are reactive systems. Software need not be reactive. Hence, the models of computation used in their respective design process need not be the same.