Math Measurement 44: Fill & Download for Free

The short answer is that they are really, really small.Here’s a diagram of a chip I made in college. I apologize for the poor quality; it’s a screen shot from some decidedly 90s-era software.If memory serves, this chip had around 1200 transistors of my own on it, and several more in the pad frame. As you can see, my design has a lot of white-space. The pad frame can actually hold more like 3500 transistors. They all fit side by side on this sliver of silicon.(EDIT: Based on other contemporary measures, it appears more like 7,500 transistors should be reasonable inside the area provided. It would require tighter layout than us first-timer undergrads were managing. I’ve tweaked some of the wording and calculations below based on better measurements.)I drew the design in 2 micron technology, which means the gate length of a minimum-sized transistor is 2 μm. That 2 micro-meters. The whole chip was around [math]2.2mm \times 2.3mm[/math], with about [math]1.8mm x 1.8mm[/math] of usable space inside. (Approx [math]3.2mm^2[/math] Go grab a ruler and look at how big 2mm is—it’s about the thickness of 2 credit cards. So imagine projecting that picture above into something about this size: [math]\Box[/math].And yet, I could fit ~1200 transistors in that space with plenty of room to spare. 2 micron means I drew features in multiples of 1μm (a unit referred to as lambda or λ). All of my transistors were itty-bitty rectangles that are [math]2\lambda[/math] long and [math]8\lambda[/math] to [math]16\lambda[/math] wide (or larger!), drawn over much larger rectangles of N and P diffusion. The smallest gate length was [math]2\lambda = 2\mu m[/math], which is why the technology was called 2 micron despite the fact features were drawn on a [math]1 \mu m[/math] grid.For example, here’s one of my inverters, with a [math]8\lambda \times 2\lambda[/math] N transistor on the left, and a [math]16\lambda \times 2\lambda[/math] P transistor on the right.Key:The green area is N diffusion.The brown area is P diffusion.The reddish color is polysilicon. Where polysilicon crosses diffusion, you get a transistor.The light blue is Metal 1.The purplish color is Metal 2. (Not seen in the inverter, but present in the whole-chip picture above.)The boxes with Xs in them are contact points between layers, aka. vias.To give you a sense of scale, the reddish rectangle is [math]2\lambda[/math] tall, and the whole inverter is about [math]14\lambda \times 44\lambda[/math]. Since [math]1\lambda = 1\mu m[/math], that’s really, really tiny: [math]14\mu m \times 44\mu m = 616 \mu m^2 = 0.000616 mm^2[/math].And if you want something more substantial to look at, here’s one of my D-flip-flops, built out of clocked set-reset flip-flops in a master-slave configuration. A quick back-of-the-napkin estimate puts its area around [math]10000\mu m^2 = 0.01mm^2[/math], and if I counted correctly, there’s 36 transistors.I had a lot of fun laying that out. :-) If I could make the entire design this dense (ie. no wires), you could fit around 11,000 transistors on the die, and more if you use minimum-sized transistors. Realistically, wires take a ton of space, and you definitely don’t want all your transistors to be minimum-sized. I had some largish transistors in my clock tree, for example.Now, 2 micron is positively barbaric technology by today’s standards. Modern leading edge chips are built from 14 nanometer technology, with 10nm and 7nm on the way. So, while my little cookie had a gate length of [math]2 \times 10^{-6}m[/math], modern chips are more like [math]14 \times 10^{-9}m[/math], which is a factor of ~140 smaller. Now, that’s 140 smaller in one dimension. Both dimensions shrink, and so to a first order, you can fit about [math]140^2 \approx 20000[/math] times as many transistors in the same space. (Note: It’s not a perfect comparison, as modern chips have more levels of metal, and so can pack things more densely as well.)2.2mm x 2.3mm is positively tiny for a chip. My chip was approx. [math]5mm^2[/math], (although my usable area was only [math]3.2mm^2[/math]), while modern processors range from [math]150mm^2[/math] to over [math]300mm^2[/math] (at least according to this page). A [math]150mm^2[/math] die has 30 times the area to work with.So, take 30 times the area and 20,000 times the density, and you’re at about 600,000 times the transistor count. If we assume we can get 7500 transistors into [math]5\mu m[/math], then we have: [math] 600000 \times 7500 = 4500000000[/math].By the link I gave above, that looks to be in the ballpark: For a 22nm, [math]177mm^2[/math] Haswell, they show 1.4 billion transistors. Going from 22nm to 14nm should give [math]2.5\times[/math] the capacity (approximately), which gives 3.5 billion transistors. So, 4.5 billion transistors in [math]150mm^2[/math] at 14nm is in the ballpark, although it’s maybe a little on the high side. The exact number you’ll get depends on transistor sizing and logic density/utilization, anyway.Thus, we get to these crazy transistor counts by two means:Make the transistors as tiny as we possibly canMake the die as large as is practicalNow, how do we go about making such tiny transistors? That’s a whole ‘nother topic.

The area of a triangle of sides 33, 44 and 55 cm is 726 cm² (Heron's formula), but if we calculate the height corresponding to the side measuring 44 cm, it comes out to be 33 cm. These results violate the Pythagorean theorem. How can this be possible?Answer:Given: A triangle who’s sides are 33 cm, 44 cm, and 55 cm and has an area of 726 sq cm.By looking at the side numbers (33,44, and 55), it appears that we have a 3–4–5 right triangle.let base(b) = 33 and height(h) = 44Area(A) = (1/2)(b)(h)A = (1/2)(33)(44)A = 726 sq cm>>>> ck goodPythagorean theorem: hypotenuse(c) = [math]\sqrt{ base^2 + height^2}[/math]c = [math]\sqrt{ 33^2 + 44^2}[/math]c = [math]\sqrt{ 3025}[/math]c = 55 cm>>>> ck goodI don’t see the problem, Pythagorean theorem is not being violated formula for finding area works.

The Einstein field equations for General Relativity which may be written in the form:[1]where:[math]R_{\mu\nu}[/math] = the Ricci curvature tensor that is constructed from themetric tensor ([math]g_{\mu\nu}[/math]) and its first and second derivatives,[math]R[/math] = the scalar curvature constructed from [math]g_{\mu\nu}[/math] and [math]R_{\mu\nu}[/math] ,[math]g_{\mu\nu}[/math] = the metric tensor which is used to measure properdistances in curved space-time,[math]\Lambda[/math] = the cosmological constant, it may represent the Dark Energy,[math]G[/math] = Newton’s gravitational constant,[math]c[/math] = the speed of light in vacuum, and[math]T_{\mu\nu}[/math] = the stress–energy tensor — this is how the mass,energy, pressure and stress is the source of gravitation.(from Einstein field equations – Wikipedia)This equation predicts how 4 dimensional space-time becomes curved in the presence of mass-energy. It explains the force of gravity and in the limit of weak curvature reproduces Newtons laws of inverse square gravity. It predicts the existence and properties of black holes and it applies to the universe as a whole. For example, this equation determines how the geometry of the universe has evolved from the Big Bang to now and will apply to the far distant future. The cosmological constant, for example, is one possible model for Dark Energy. Thus it covers everything from black holes to the entire universe as a whole. The only places where it is believed to break down is near the singularity at the center of black holes and at T=0 in the Big Bang. But for T > the Planck Time [math](5 \times 10^{-44} seconds)[/math] to the end of the universe this equation should be accurate. Now to me, that is beautiful!