Eec Work Verification: Fill & Download for Free

Top U.S. research university in EDA(Section #1)UC Berkeley EECS is a clear winner by far.Their research spans from electronic system-level (ESL) design and verification to technology CAD (TCAD). No other research university has that range of research teams/labs/groups that span so many EDA topics. The collaborators of UC Berkeley's faculty and students include many of their alumni, the academic descendants of Berkeley EECS alumni, and industry and academic collaborators from all over the world. Two of their faculty members, Prof. Alberto Sangiovanni-Vincentelli and the late Prof. A. Richard Newton contributed greatly to the founding of two of the three giants in electronic design automation (EDA): Synopsys (company) and Cadence Design Systems (company). Their alumni have become successful faculty members in world-class research universities, like MIT and Stanford. Their graduate classes in EDA also span from TCAD (e.g., device modeling) and physical design to logic synthesis and verification, and also from ESL design and cyber-physical systems (CPS) to Bio Design Automation and VLSI formal verification (e.g., sequential equivalence checking).Good U.S. research universities in EDA(Section #2)Off the top of my head, other good research universities that have good EDA labs (at least 2-3 faculty members working in EDA) and multiple graduate-level EDA classes include (not listed in any order):University of Michigan: physical design, logic synthesis, EDA for quantum computing, logic verification, and post-silicon debugging. Prof. Igor Markov is a professor at Michigan's EECS department.Massachusetts Institute of Technology: Numerical techniques (e.g., nonlinear Model Order Reduction, integral equation solvers) for EDA, including circuit simulation, interconnect modeling, and layout/parasitic extraction; check out the Computational Prototyping Group at MIT's legendary Research Laboratory of Electronics (RLE). Prof. Arvind and Prof. Srini Devadas have worked on problems in ESL, and logic synthesis and logic verification.Carnegie Mellon University. They work on problems in analog/RF and mixed-signal (AMS/RF) CAD, Design for Manufacturability (DFM), EDA tools for network-on-chips (NoC)... They also have graduate classes in physical design and logic synthesis/verification.Cornell University: EDA tools for Asynchronous Circuits, TCAD, physical design, ESL, VLSI testingGeorgia Institute of Technology: Nanoscale 3-D physical design and circuit simulation (or rather, numerical techniques for EDA).Northwestern University: physical design, thermal-aware EDA tools, and FPGA CAD tools.Purdue University: VLSI testing, and a range of topics addressing nanoscale challenges concerning variability and reliability, model order reduction for VLSI circuits and systems, physical design, and interconnect modeling.Stanford University: range of "non-traditional" EDA projects spanning multiple traditional EDA topics, TCAD, EDA tools addressing reliability concerns, and VLSI testing. They also used to work on VLSI formal verification.Texas A&M University (TAMU): Physical design, numerical techniques for EDA (including power grid verification) and AMS/RF CAD, NoC, EDA tools addressing fault-tolerance, DFM, logic synthesis, and ESL... Texas A&M University (TAMU) is not as famous as the other universities, but it does produce stellar research papers. For example, Prof. Peng Li has won 4 best paper awards at Design Automation Conference (DAC) and International Conference on Computer-Aided Design (ICCAD) in the last 10 years, which is 20% of the best paper awards for DAC and ICCAD in this time frame.University of California, San Diego: DFM, physical design, ESL, and VLSI testingUniversity of California, Los Angeles: physical design, logic synthesis, ESL (including high-level synthesis), DFM, and numerical techniques for EDA (including model order reduction and interconnect modeling).The University of Texas at Austin: DFM, physical design, VLSI formal verification, VLSI testing, and TCADAlso, see Choosing a Graduate Program in VLSI Design & Related Areas: Things to Consider.Competitive U.S. research universities in EDA (Honorable Mention)(Section #3)Honorable mention:University of Illinois at Urbana-Champaign: numerical techniques for EDA (including model order reduction, layout/parasitic extraction, and interconnect modeling)... I may be wrong, but I reckon they have other stuff. However, they do not seem to be prominent in EDA, even though UIUC is a world-class research university.Brown University: EDA tools for thermal analysis/design, VLSI testing, and some other topicsBoston University: There are 2-3 faculty members working in EDA there, including Prof. Douglas Densmore work works in Bio Design Automation.University of California, Irvine: Has a strong research lab/group in ESL, including high-level synthesisUniversity of California, Riverside: numerical techniques for EDA (including model order reduction, layout/parasitic extraction, and interconnect modeling), application-specific instruction-set processor (ASIP) synthesis and design methodologies, and low-power EDA. They may have professors working on ESL and logic synthesis, too.University of California, Santa Barbara: VLSI testing, logic verification, and physical design. They may also be working on logic synthesis.University of Southern California: physical design, physical synthesis, logic synthesis, logic verification, EDA tools for Asynchronous Circuits, EDA for Quantum Computing, ESL, VLSI testing, EDA tools for low-power design, and NoC.University of Minnesota - Twin Cities: physical design and physical synthesis, logic synthesis and verification, and numerical techniques for EDA (to some extent)The University of Utah: Design automation for Cyber-Physical Systems, Bio Design Automation, EDA tools for Asynchronous Circuits, and VLSI formal verificationUniversity of Wisconsin - Madison: physical design, physical synthesis, DFM, EDA for reconfigurable logic (e.g., FPGA), post-silicon debugging, low-power EDA tools, EDA tools for fault-tolerance, and VLSI testingSufficiently Competitive U.S. research universities in EDA(Section #4)Other research universities that may interest you:Arizona State University: Strong TCAD group in device modelingColumbia University: EDA tools for Asynchronous CircuitsDuke University: Design automation for Microelectromechanical systems (MEMS) (microelectromechanical systems) and digital microfluidic devices (biomedical devices), and VLSI testingUniversity of Arizona: A bunch of faculty members in VLSI testing, interconnect modeling, DFM, NoC, among other thingsUniversity of California, Davis: ESL groupUniversity of California, Santa Cruz: physical design groupUniversity of Massachusetts, Amherst: Kinda like University of Arizona; it has a bunch of decent faculty members working on different things... TCAD, VLSI testing, and EDA for reconfigurable logic (e.g., FPGA)University of Notre Dame: ESL???University of Pennsylvania: EDA tools for nanoscale reconfigurable logicUniversity of Rochester: Lone maverick working on numerical techniques for EDA (e.g., interconnect modeling), physical synthesis, physical design, and AMS/RF CADIowa State University: Physical designColorado State University (specifically, Colorado State University ): ESLAuburn University: VLSI testing. TCAD, and computational electromagneticsUniversity of Maryland, College Park: TCAD, approximate computing, energy-efficient EDA tools, and DFMNorth Carolina State University: AMS/RF CAD, and random topics in EDA, just like University of Massachusetts, Amherst and University of ArizonaUniversity of North Carolina at Chapel Hill: EDA tools for Asynchronous CircuitsStony Brook University: ESL and AMS/RF CADPortland State University (Portland State University): VLSI formal verification, VLSI testing, and ESL (and Bio Design Automation???)University of Pittsburgh: mixed-technology design automation tools, including design automation tools for OptoelectronicsSouthern Methodist University: VLSI testing, logic synthesis, and logic verificationDrexel University: physical design and NoCDecent/"Decent" U.S. research universities in EDA(Section #5)If you can't get into the aforementioned universities, here are some other universities that may be of interest to you. They have at least one lone faculty member working in EDA.Southern Illinois University CarbondaleUniversity of IowaUniversity of Maryland, Baltimore County (UMBC): Power modelingMichigan State University: Computational electromagneticsMichigan Technological University: TCAD and numerical techniques for EDAMissouri University of Science & Technology: electromagnetic compatibility, like signal integrity analysisUniversity of North Carolina at Charlotte: AMS/RF CADUniversity at Buffalo: VLSI testingUniversity of Cincinnati: lone ranger working on digtial EDA, who had worked on AMS/RF CAD tools.Utah State UniversityThe University of Texas at San Antonio: physical design, DFM, and physical synthesisUniversity of North Texas: AMS/RF CAD based on meta-heuristicsIllinois Institute of Technology Chicago - Illinois Tech: power grid simulation of Very-Large-Scale Integration systemsUniversity of South CarolinaWell, if you are considering these places, you may as well check out opportunities in Europe (e.g., see Computer Science Programs in Europe, Pasquale Ferrara's answer to When recruiting Software Engineer/Computer Science majors for US companies, what international universities are on par with MIT/Stanford?, and Pasquale Ferrara's answer to Which university is best to recruit computer science majors from and why?) and Taiwan (e.g., National Taiwan University and National Tsing Hua University). Also, Federal University of Rio Grande Do Sul (UFRGS) is also making some noise in EDA in Porto Alegre, Brazil. Korea Advanced Institute of Science and Technology (KAIST) (and perhaps Seoul National University) seems like a reasonable choice.For graduate programs in EDA, I would strongly recommend that you do not go to graduate school in India, Singapore, or Australia.If you want me to make a recommendation, if you cannot get into a good/competitive U.S. research university in EDA (see sections 1-3, or perhaps sections 1-4), it may be worth your while to go look at other competitive research universities outside the U.S., such as National Taiwan University (NTU). NTU has done well (placed top 3 regularly in the last 5 years) in EDA programming/research contests, such as the ISPD programming contest and the CADathlon (held before the start of ICCAD). See Learning about Physical Design outside of National Taiwan University about my blog post titled, “Learning about Physical Design outside of National Taiwan University.”

If you refer to integrated circuits (ICs) as hardware, the main challenge (as Dan Zhang mentioned) is technical expertise.Next, tools supporting IC design and verification, which are known as electronic design automation (EDA) software, cost a lot! Tools for VLSI routing and placement can cost half a million US dollars per software license. Open source tools are highly inadequate for addressing today's challenges with advanced nanoscale semiconductor manufacturing processes.Analog and mixed-signal IC design is an art. There are probably tens of thousands of IC design engineers who can do this. Contrast that to hundreds of thousands of digital IC/VLSI design (+ verification and post-silicon validation) engineers, who work through the stack (architectural-level to transistor-level); this does not include device engineers and CAD engineers, who manage the VLSI design flow.Also, with digital VLSI design, there is a range of engineers who need to be good at continuous math (say with signal integrity analysis) to those who are good at circuit complexity and partitioning (discrete math).To complicate things further, VLSI design is becoming more like software development. VLSI design and verification engineers write lots of code in SystemC, SystemC-AMS, SystemVerilog, Verilog-A, Verilog-AMS, VHDL, VHDL-AMS, Perl, Tcl, Python, MATLAB, C, and C++. For people to do this, they need a good background in electrical and computer engineering (ECE), or electrical engineering and computer science (EECS).By hardware, if you are referring to processors, processor design is typically undertaken by people with a strong background in computer engineering who are good at computer architecture, VLSI design, operating systems, and compiler design. It's hard to develop such background, since most ECE/EECS programs do not offer enough challenging projects for students in these areas. Even if they do, a lot of students would avoid taking graduate-level classes (in the US high education system) in all of these areas.Otherwise, if you are referring to the electronics (in general, such as the printed circuit board) and the mechanical chassis, it is very hard to analyze such "hardware" holistically, by running analyses for electromagnetic interference/compatibility, thermal analysis, noise analysis, signal integrity analysis, power analysis, mechanical stress analysis, and what not. Typically, engineers use expensive CAD tools for these activities.In short, the lack of expertise and the steep learning curve in designing interesting ICs and processors as well as developing EDA tools make open source hardware design/development challenging, exclusive, and intimidating. Having better open source EDA tools can help. However, people still need a strong ECE or EECS background to do VLSI or processor design.

It depends on what do you mean by ASIC/FPGA/VLSI verification, henceforth denoted as VLSI verification.If you are concerned about the methodology, well, guess what? The verification methodology partially, if not mostly, depends on the availability and capabilities of the verification point tools. Hence, there is only so much work you can do with respect to VLSI verification methodology for a given set of verification tools.However, if you have a good background in electrical engineering (EE), based on the definition of the U.S.-based Accreditation Board for Engineering and Technology (ABET), and computer science (CS), you can choose to work on the VLSI verification tools and VLSI verification methodology. which can be modified by the tools that you develop. Note that the ABET definition contains a considerable amount of computer engineering, power engineering, control engineering, analog and mixed-signal IC design and testing, and other common EE research areas such as signal processing and telecommunications.If you do not have a strong EECS (EE + CS) background, developing decent VLSI verification tools can be very challenging.As we make a push for more mixed-signal SoCs, the demand for VLSI verification tools and methodologies to address mixed-signal VLSI systems will increase. This would go beyond traditional circuit simulation tools, and can be modified and extended for cyber-physical systems (which are hybrid systems, just like mixed-signal circuits).Some universities focus on the computational engines of the VLSI verification tools, such as the model checkers, equivalence checkers, and theorem provers. Examples of such computational engines are SAT solvers and SMT solvers. The University of Trento in Trento, Italy has a world-class team working on the MathSAT SMT solver.For VLSI formal verification, UC Berkeley's ABC tool is capable of sequential equivalence checking and sequential logic synthesis. VLSI/hardware model checking has a bunch of categories. So, I would look at the results of the hardware model checking competition. See Hardware Model Checking Competition 2011. As for hardware/VLSI theorem proving, it has yet to gain adequate traction/acceptance.There are some universities that work on semi-formal verification, particularly assertion-based VLSI verification. Generally, the tool development is not that fancy, except perhaps for assertion synthesis of industry-grade VLSI systems (hard to prove in academia). Personally, I would avoid this.For logic simulation, look at those that are based on parallel computing (i.e., based on GPGPU computing or many-core processors). University of Michigan was recently working on this.For circuit simulation, see UC Berkeley, UC Riverside, and University of Toronto.Also, pay attention to other forms of verification, such as timing verification (including SSTA, statistical static timing analysis) - University of Michigan, power verification (for power sign-off), DFM sign-off tools, thermal sign-off/analysis (UCSD, or UC San Diego), and what not.