Dual Notice Of Address: Fill & Download for Free

In a word: cost.DRAM fundamentally has a lower marginal cost per bit than SRAM. It uses fewer transistors per bit (one transistor + capacitor, vs six transistors), and so you can fit way more DRAM bits into the same amount of silicon.DRAM had three main fixed overhead costs that SRAM didn't:Multiple voltage supply rails. -5V, +5V, and +12V for 4116 DRAM, for example.Refresh.Multiplexed addressing.From a MOSTEK 4116 datasheet:You can see it all in that pinout. Well, maybe not refresh, unless you happen to know about [math]\overline{\texttt{RAS}}[/math]'s dual purpose.All three of these contribute to system cost. Early microprocessors sometimes needed multiple voltage supplies, but most quickly went to single-rail +5V. Digital logic wasn't very integrated, so you needed a fair bit of discrete TTL to manage refresh and multiplexing.Here's a 4K SRAM card from MITS, maker of the famous Altair that Microsoft launched its BASIC on:(Image source.)Compare this to their 4K DRAM board:(Image source.)Notice the SRAM board chip count is dominated by SRAM chips. That's the big 8 × 4 array of chips at the left. The logic section at the right is quite small. In contrast, the DRAM board is dominated by logic. The DRAM itself is just a thin column of 8 chips at the right.On the supply rails front, DRAM lagged a little behind other discrete logic chips.* The 16K × 1 chips still wanted 3 voltages. By the time you get to the 4164, though (64K × 1-bit), DRAM caught up and only needed a single rail.As transistors became cheaper, it became easier to integrate the refresh and address multiplexing logic into system level controllers. The Z-80 had anticipated that trend by integrating a 7 bit refresh counter on chip. That sadly didn't scale to the 64K DRAMs when they arrived that want an 8-bit counter.By the time you get to the 64K era, the fixed overheads of DRAM were absorbed and the marginal cost per bit won the day.The cost advantages of DRAM are large enough that large capacity discrete “SRAM” chips often pseudo SRAM. It's a DRAM under the hood with an integrated controller and a simple SRAM-style bus interface. I use one of those in my Intellivision flash cart.True SRAM still has two main advantages over DRAM:Static power (assuming CMOS), including retention power.Speed.Thus, you still find SRAMs—sometimes several megabytes worth—on chip. Processor caches are built out of SRAM. Embedded processors may have significant amount of addressable SRAM, etc.Low standby retention power is what made SRAM a great fit for the Tandy TRS-80 Model 100 portable. Its SRAM could be treated as non-volatile, effectively, by using a low cost, low tech battery backup.Addendum:*In terms of inconvenient voltages, MOSTEK's MK4116, and the 4K × 1-bit MK4027 that preceded it, didn't hold a candle to Intel's inaugural PMOS DRAM chips, such as the 1103.Here's a couple excerpts from the databook:The three columns in the middle are min/typ/max. And just look at those supply voltages:And remember, this is PMOS, which is why [math]V_{DD}[/math] is 0, not [math]V_{SS}[/math].So, you pump in 16V and 12V. And on the output you could get at little as 50mV for a 1, and ?? (you're on your own!) for a 0. The person who pointed me to the 1103, one of the designers of the CP1600, said it was common to use amp circuits normally associated with core memory to amplify the output and interface to other logic.Addendum 2: In case no one noticed, I did actually try to pick a picture of a $100 bill that was accurate for the time frame involved, although I grabbed one that’s too early. Now a Series 1981 bill is up there.

“After getting a diversity visa to enter the USA, can I be out from the USA without a Green Card?”Oy. Yet Another US immigration law question that arises from the fact that nobody seems to actually know what a green card is. A US “green card” is more technically any document that serves as a Form I-551, and thus serves as evidence of lawful permanent resident status. Most LPRs have a permanent green card sent to them in the mail, typically six weeks after arriving in the US. However, this is not the only document that can serve as a green card, and indeed there is one specific document that is also a green card; I’ll come to this particular point in a short while.There are, however, two things that are not a green card. One of them is an immigrant visa, issued by a US consulate, that has not yet been used to enter the United States. The other is an approved immigrant petition (regardless of which form was used to apply for it). While these represents steps toward a green card, none of them is a green card itself. I realize that a lot of people say that they’ve been “awarded a green card” to describe the process of being approved at any of the several steps along the way to becoming a lawful permanent resident, but from a legal and technical standpoint, one doesn’t actually have a green card until one is admitted to the United States as an immigrant, either by entering the US using an immigrant visa, or adjusting status to that of a lawful permanent resident via a I-485 petition.Because of this constant confusion over the difference between an immigrant visa and a green card, this question is ambiguous. There are many ways I can parse this question; I’ll address as many of them as I can think of.If you have entered the diversity lottery and learned that your entry has been selected, but have not yet started the process of applying for an immigrant visa (or for applying for adjustment of status, if you are in the United States already), you can travel without any impact on your entry. You don’t even have a petition at this point; all you have is a selected entry, and a selected entry is valid without regard to where the applicant resides. In addition, having a selected entry on which no action has been taken does not establish “immigrant intent” and thus should not impact the validity of any nonimmigrant US visas you might have.If you have entered the diversity lottery, have learned that your entry has been selected, and have initiated the process of applying for an immigrant visa, but have not yet received that visa, you can travel freely; however, your application for an immigrant visa is demonstration of immigrant intent, which may invalidate any nonimmigrant US visas you have (other than H or L visas, which allow dual intent). Traveling abroad will not affect your application. Indeed, you will have to travel abroad, to attend the consular interview, as there are no US consular facilities in the United States.If however, you have instead applied for adjustment of status, and you leave the United States before your petition is granted, without first obtaining advance parole, you will be deemed to have abandoned your petition and will likely lose your opportunity to immigrate.If you have applied for an immigrant visa through the diversity visa program and have actually received an immigrant visa after being interviewed abroad at a US consular office, but have not yet entered the United States, you are free to travel anywhere in the world without affecting your visa. Note, however, that your visa was issued with an expiration date, and if you do not use it before it expires, you will not be allowed to enter the United States using that visa. Since US consular officials, by policy, cancel all nonimmigrant visas held by an alien when issuing that alien an immigrant visa, the only way you can at this point now enter the United States is using that immigrant visa.If you have actually received an immigrant visa and used it to enter the United States, congratulations: you are now a US lawful permanent resident and, assuming you have not lost your passport, are in possession of a green card. When a first-time arriving immigrant uses the immigrant visa issued to them by a US consular official to enter the United States, the immigration officer at the inspection point endorses that visa, and by so doing converts it into a temporary green card, valid for one year. Thus, if you have been admitted as an immigrant, you automatically have a green card. USCIS will (assuming they don’t make any bureaucratic mistakes) mail you a permanent green card in six weeks or so after you arrive, but that counterstamped visa in your passport is a green card valid for one year after the date it was counterstamped and can be used to reenter the United States as a “returning immigrant”.The only situation that is a bit fuzzy is the situation in which you adjust status while in the United States. Since you did not receive an immigrant visa to be countersigned, you don’t have a temporary green card in this situation. In this case, your Form I-797, informing you that your adjustment of status petition has been approved, acts as temporary evidence of admission as a lawful permanent resident until you receive your green card. However, if you are in this situation and need to travel abroad before you receive your permanent green card, there is a specific document that USCIS can issue to you that provides more clear evidence of admission as a LPR. The notice of approval you received should state a phone number you can call to arrange for the issuance of such a document, should you need one.

This is very clearly a homework problem, but it’s an interesting one to explore. I won’t answer it for you, in part because I can’t. Nobody can, with just the information you’ve given us. The exploration below hopefully makes it clear why.Your assignment looks like it’s meant to exercise a particular instruction encoding design strategy that you covered in class. It most likely expects you to follow a general RISC-like strategy that:has easily distinguished instruction formats,minimizes the number of unique fields across instruction formats, andfits in a fixed length encoding.Unfortunately, your question does not provide sufficient information to complete this assignment, I think. Your course probably provided additional necessary context that we don't have access to. Thus, we can't work your homework properly, even if we wanted to.Let's see why I say that.Consider a general approach to instruction formats along these lines:+-------+-------+---------------+ | addr1 | addr2 | opcode_2a | fmt2a +-------+-------+---------------+  +-------+-----------------------+ | addr1 | opcode_1a | fmt1a +-------+-----------------------+  +-------------------------------+ | opcode_0a | fmt0a +-------------------------------+ An instruction decoder needs to be able to determine whether a given bit pattern falls into fmt2a, fmt1a, or fmt0a.You can think of the decoder as using a decision tree to determine the instruction format. The inputs to this decision tree are bits from the encoded instruction. The output indicates the instruction’s format. This decision tree must be unambiguous.Prioritize Zero Address Opcode Space (fmt0a)At one extreme, you heavily prioritize fmt0a > fmt1a > fmt2a in your opcode space allocation. I personally think that's a bad idea, but I leave it to you to reason about why. This first example demonstrates one way to prioritize heavily toward fmt0a:+-------+-------+-----------+---+ | addr1 | addr2 | opcode_2a |1 1| fmt2a +-------+-------+-----------+---+  +-------+-------------------+---+ | addr1 | opcode_1a |0 1| fmt1a +-------+-------------------+---+  +-----------------------------+-+ | opcode_0a |0| fmt0a +-----------------------------+-+ This example uses a fixed prefix in the lower 1 or 2 bits to indicate the format. The opcode fields in each format are otherwise unconstrained, except by their width.Prioritize Two Address Opcode Space (fmt2a)At the other extreme, you prioritize fmt2a > fmt1a > fmt0a. This makes more sense to me. Again, contemplate on why.This second example demonstrates one way to prioritize heavily in favor of fmt2a:+-------+-------+---------------+ | addr1 | addr2 | opcode_2a | fmt2a +-------+-------+---------------+  +-------+-------+---------------+ | addr1 | op_1a | (zeros) | fmt1a +-------+-------+---------------+  +-------+-----------------------+ | op_0a | (zeros) | fmt0a +-------+-----------------------+ In this example, opcode_0a exactly overlaps addr1, and opcode_1a exactly overlaps addr2. This makes the opcode fields exactly as wide as the address fields they overlap.Notably, opcode_0a, opcode_1a, and opcode_2a end up without any overlapping bit assignments. You could almost think of combining the three formats into one format with dual-purpose fields:+-------+-------+---------------+ | addr1 | addr2 | | | op_0a | op_1a | opcode_2a | +-------+-------+---------------+ Given that, you can look at the opcode_2a and opcode_1a fields to determine which instruction format is active, before you know which format is actually active. This example uses the all-zero opcodes in fmt2a and fmt1a to escape to fmt1a and fmt0a, respectively.fmt2a: opcode_2a != 0fmt1a: opcode_2a == 0 && opcode_1a != 0fmt0a: opcode_2a == 0 && opcode_1a == 0This scheme allocates noticeably more opcode space for fmt2a, leaving much less opcode space for fmt1a and fmt0a.Questions:How much larger is the opcode space for fmt2a in the second example vs. the first?How much smaller did the opcode spaces for fmt1a and fmt0a become?A More Flexible ApproachA practical instruction set likely falls somewhere between those extremes. Suppose I allow the opcode_1a and opcode_0a fields to be wider, but otherwise follow the second example’s framework:+-------+-------+---------------+ | addr1 | addr2 | opcode_2a | fmt2a +-------+-------+---------------+  +-------+-----------+-----------+ | addr1 | opcode_1a | (zeros) | fmt1a +-------+-----------+-----------+  +-----------+-------------------+ | opcode_0a | (zeros) | fmt0a +-----------+-------------------+ Questions:What are the relationships between the opcode spaces in this generalized example?In particular, how do you determine which Instruction format is active now?As you increase the width of opcode_0a, what is its impact on fmt1a and opcode_1a? Likewise for opcode_1a vs. fmt2a and opcode_2a.Is there ever any advantage to making opcode_0a narrower than addr1? Why or why not? Likewise for opcode_1a vs. addr2.Other ConsiderationsA practical instruction set architecture typically supports a wider range of operand types than abstract “addresses." Such an architecture likely needs additional instruction formats to accommodate the full range of operand and instruction types.Examples:Immediate constantsRelative addresses for branchesIndirect addressesThree address instructions, possibly operating only on a subset of the address rangeOperands constructed from pairs of adjacent addressesDifferent kinds of address: general purpose register vs. data memory vs. processor control/status registerBonus Exercise:If you really, really want to prioritize the opcode space available to fmt0a over the other formats, you can go even further than I did in my first example above. This is why I said “heavily prioritize” rather than “strictly prioritize” in that example.If you dedicate as much opcode space as possible to fmt0a, you might end up with something like this:+-------+-------+-------------+-+ | addr1 | addr2 | (zeros) |1| fmt2a +-------+-------+-------------+-+  +-------+-----------------------+ | addr1 | (zeros) |0| fmt1a +-------+-----------------------+  +-------------------------------+ | opcode_0a | fmt0a +-------------------------------+ Now, fmt2a and fmt1a have each been reduced to a single all-zeros opcode each.Questions:How many opcodes are available for opcode_0a in fmt0a now?Hint: What encodings are not available to opcode_2a, because they correspond to fmt1a or fmt2a prefixes?What are the advantages and disadvantages of this encoding?Could you devote even more opcodes to fmt0a, by placing restrictions on addr1 and/or addr2? If, for example, you weren't required to access address 0, how many more opcodes could you devote to fmt0a?Remember: your original homework asked how many zero operand instructions were possible. Let's pull out all the stops!P.S. You'll notice I didn't indicate field widths in any of my examples. I did that on purpose. You must derive those from the problem statement.